Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2007-05-09
2009-08-04
Monbleau, Davienne (Department: 2893)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C257S774000, C257SE21229
Reexamination Certificate
active
07569486
ABSTRACT:
A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i.e., remove resist over, a huge via feature area causing under layer dip.
REFERENCES:
patent: 6743713 (2004-06-01), Mukherjee-Roy et al.
patent: 7232748 (2007-06-01), Ali
Choi Yong Seok
Jacques Jeannette Michelle
Brady III Wade J.
Harrison Monica D
Monbleau Davienne
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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