Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-08-07
1998-12-29
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711128, G06F 1502
Patent
active
058549439
ABSTRACT:
A cache output selector for a multi-way set-associative cache memory which provides for simultaneous access of multiple-word data is presented. The cache memory comprises a plurality of data arrays wherein no two consecutive multiple-word reside in the same data. The cache output selector of the present invention includes, for each data array of the plurality of data arrays, a qualifying multiplexor which receives the respective tag match signals from each of the tag matching circuits as data input and a set selector signal, as selector input, and at least one qualifying signal as qualifying input. The set selector signal indicates which data array a first set of the multi-way set-associative memory resides in during a current read/write cycle. The qualifying multiplexor combines a clock qualifying functionality and a multiplexor functionality to produce a data array output enable signal in only two levels of logic. The cache memory comprises a prefetch buffer path and a bypass path from which the cache output selector selects an addressed multi-word for output. The output path selected circuit includes a pair of qualifying NOR gates. Each qualifying NOR gate combines a clock qualifying functionality and a logical NOR functionality to produce a qualified prefetch buffer path output enable signal and a qualified bypass path output enable signal respectively.
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McBride John G.
Ziemkowski Ted B.
Hewlett--Packard Company
Lee Felix B.
Swann Tod R.
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