Speculatively performing read transactions

Details Speculatively performing read transactions Speculatively performing read transactions

2006-03-29

2009-10-06

Song, Jasmine (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S138000, C711S141000, C711S167000

Reexamination Certificate

active

07600078

ABSTRACT:
In one embodiment, the present invention includes a method for speculatively providing a read request to a memory controller associated with a processor, determining coherency of the read request in parallel with obtaining data of the speculatively provided read request, and providing the data of the speculatively provided read request to the processor if the read request is coherent. In this way, data may be used by a processor with a reduced latency. Other embodiments are described and claimed.

REFERENCES:
patent: 6009488 (1999-12-01), Kavipurapu
patent: 6993633 (2006-01-01), Sakakibara et al.
patent: 2002/0087811 (2002-07-01), Khare et al.
patent: 2004/0044850 (2004-03-01), George et al.
patent: 2005/0240734 (2005-10-01), Batson et al.
U.S. Appl. No. 10/833,963, filed Apr. 27, 2004, entitled “A Two-Hop Cache Coherency Protocol” by Ling Cen.

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