Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2007-08-08
2009-08-18
Pham, Ly D (Department: 2827)
Static information storage and retrieval
Read/write circuit
Signals
C365S194000, C365S210100, C711S167000
Reexamination Certificate
active
07577049
ABSTRACT:
A computer memory includes a sense enable control module for generating a sense enable signal for a memory core. The sense enable control module includes an active side for transmitting the sense enable signal for the memory core, and a calibration side for determining when the sense enable signal is to be transmitted by the active side. Both the active side and the calibration side are defined to receive a timing signal. The active side is defined to transmit a delayed version of the timing signal as the sense enable signal for the memory core. The calibration side is defined to adjust the delay amount associated with the delayed version of the timing signal to be transmitted by the active side based on a determined sufficiency of the delay amount.
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Martine & Penilla & Gencarella LLP
Pham Ly D
Tela Innovations, Inc.
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