Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-04-19
2011-04-19
Patel, Hetul (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C712S207000
Reexamination Certificate
active
07930485
ABSTRACT:
A system and method for pre-fetching data from system memory. A multi-core processor accesses a cache hit predictor concurrently with sending a memory request to a cache subsystem. The predictor has two tables. The first table is indexed by a portion of a memory address and provides a hit prediction based on a first counter value. The second table is indexed by a core number and provides a hit prediction based on a second counter value. If neither table predicts a hit, a pre-fetch request is sent to memory. In response to detecting said hit prediction is incorrect, the pre-fetch is cancelled.
REFERENCES:
patent: 5778436 (1998-07-01), Kedem et al.
patent: 6282614 (2001-08-01), Musoll
patent: 6401193 (2002-06-01), Afsar et al.
patent: 6457101 (2002-09-01), Bauman et al.
patent: 6865652 (2005-03-01), Pencis et al.
patent: 7003633 (2006-02-01), Glasco
patent: 7103725 (2006-09-01), Glasco
patent: 7107408 (2006-09-01), Glasco
patent: 7434004 (2008-10-01), Spracklen et al.
patent: 7487296 (2009-02-01), Iacobovici et al.
U.S. Appl. No. 11/877,311, filed Oct. 23, 2007.
Conway Patrick
Fertig Michael K
Lepak Kevin Michael
Yuan Cissy Xumin
Globalfoundries Inc.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Patel Hetul
Rankin Rory D.
LandOfFree
Speculative memory prefetch does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Speculative memory prefetch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Speculative memory prefetch will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2717048