Speculative bus cycle acknowledge for 1/2X core/bus clocking

Details Speculative bus cycle acknowledge for 1/2X core/bus clocking Speculative bus cycle acknowledge for 1/2X core/bus clocking

1998-06-02

1999-12-28

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

710109, G06F 106, G06F 1314

Patent

active

060095334

ABSTRACT:
In a microprocessor, a speculative acknowledge/rescue scheme is implemented in the bus controller to increase bus cycle performance for 1/2X clocking. For the odd cycles of the bus controller clock that result from 1/2X clocking, bus cycle requests from the cache controller, which ordinarily cannot be acknowledged in the same bus controller clock as received (even though the bus cycle can still be run the that clock), are speculatively acknowledged. If the bus controller cannot run the bus cycle in that clock, rescue is initiated in which the bus cycle request is resubmitted in the next clock. In an exemplary embodiment, snoop write back requests are prioritized such that a pending rescue bus cycle will be stalled until the snoop write back request is completed. The speculative acknowledge/rescue scheme is advantageous in minimizing any adverse impact on performance by minimizing the number of unacknowledged bus cycle requests during odd clock cycles created by 1/2X clocking.

REFERENCES:
patent: 5276818 (1994-01-01), Okazawa et al.
patent: 5396599 (1995-03-01), Cobbs et al.
patent: 5621901 (1997-04-01), Morriss et al.
patent: 5623646 (1997-04-01), Clarke
patent: 5742847 (1998-04-01), Knoll et al.

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