Specifying wrap register for storing memory address to store...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral monitoring

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C710S006000, C710S059000, C712S214000

Reexamination Certificate

active

06275876

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to computer architectures, and more particularly to a system and method for storing the status of an operation in memory.
BACKGROUND OF THE INVENTION
Computing systems typically include a processor and a memory associated with the processor. Often, the computing systems are electrically connected to external devices, such as disk drives, scanners, or monitors. The computing system usually includes a software program containing numerous commands. The processor executes the commands from the software program. In some applications, the software program uses programmed input/output (PIO) instructions via the processor to communicate with the external devices. The software program issues a first PIO instruction to the processor to communicate with a first external device. PIO instructions are typically characterized as synchronous. By the term “synchronous,” it is meant that the processor does not proceed to a second PIO instruction issued by the software program until the first PIO instruction has been completed and an associated completion status signal is transmitted to the processor that issued the first PIO instruction.
In some applications, the use of PIO instructions is advantageous because the software program receives immediate feedback of whether the desired operation with the external device was completed successfully; however, PIO instructions have disadvantages. One such disadvantage is that PIO instructions often result in degraded processor performance because the total length of time it takes to deliver, execute, and transmit a completion status signal for the overall operation is time consuming. This performance degradation increases as the processor speed increases and as the external devices are placed in physical enclosures that are located remotely from the system processor.
Another method used by software programs to communicate with external devices is by issuing memory mapped input/output (MMIO) instructions. As MMIO instruction is an instruction that the processor uses to access the main memory. The processor typically does not distinguish between MMIO instructions to external devices and MMIO instructions to main memory. MMIO instructions are asynchronous. By the term “asynchronous,” it is meant that the processor executes a second sequential MMIO instruction without waiting for an associated completion status signal from the external device being delivered back to the system processor for the first MMIO instruction. Thus, where data flows only from the processor to the external device, the processor does not wait for a return completion status signal, and communication with the external device does not have a negative impact on the processor's performance.
MMIO instructions also have disadvantages. One disadvantage of MMIO instructions is that the software program does not receive feedback on the status of the operation from the external device. This may lead to unrecoverable errors or undetected data loss. To overcome this disadvantage, in some applications, the completion status of an MMIO instruction is determined by reading a status register in an input/output bus controller or in the external device itself. Reading a status register in the input/output bus controller or in the external device also comes with problems. The processor must wait for the read operation to complete and must typically wait for the completion of previous MMIO instructions. Thus, the processor typically stops execution of subsequent MMIO instructions until the read operation and the previous MMIO instruction are completed. Thus, reading a status register negates the advantage of MMIO instructions and degrades processor performance similar to PIO instructions.
Therefore, improvements in the execution of input/output instructions are desirable.
SUMMARY OF THE INVENTION
In one aspect of the present invention, one example embodiment involves a computing system including a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address from the processing system. The control system communicates the first instruction set received from the processing system to an external device. The control system receives the first completion status from the external device, accesses the first register to determine the first address for the first instruction set, and stores the first completion status in the determined first address.
In another aspect of the present invention a method of storing completion statuses in described. The method includes generating a first instruction set and a first address for storing a first completion status for the first instruction set; receiving the first address from a processing system in a first register; communicating the first instruction set received from the processing system to an external device; receiving the first completion status from the external device; accessing the first register to determine the first address for the first instruction set; and storing the first completion status in the determined first address.
The above summary of principles of the disclosure is not intended to describe each illustrated embodiment or every implementation of the present disclosure. The figures and the detailed description that follow more particularly exemplify certain preferred embodiments utilizing the principles disclosed herein.


REFERENCES:
patent: 4535404 (1985-08-01), Shenk
patent: 5504869 (1996-04-01), Uchida
patent: 5603066 (1997-02-01), Krakirian
patent: 5678062 (1997-10-01), Okada et al.
patent: 5809333 (1998-09-01), Story et al.
patent: 6199187 (2001-03-01), Tamura et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Specifying wrap register for storing memory address to store... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Specifying wrap register for storing memory address to store..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Specifying wrap register for storing memory address to store... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2499449

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.