Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2000-06-21
2004-05-11
Kim, Kenneth S. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Branching
C709S241000, C710S267000, C710S269000, C714S034000
Reexamination Certificate
active
06735690
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to improved techniques for processor event detection and action specification using a generalized mechanism.
BACKGROUND OF THE INVENTION
A processor event or p-event may be defined as some change of state that it is desirable to recognize. The acknowledgement of a processor event may be termed a processor action or p-action. The purpose of the event-action mechanism, or eventpoint, is to synchronize various actions with specific program and/or data flow events within the processor. Examples of eventpoints which may be encountered include reaching a specified instruction address, finding a specific data value during a memory transfer, noting the occurrence of a particular change in the arithmetic condition flags, accessing a particular memory location, etc. Eventpoints can also include a linked sequence of individual eventpoints, termed chaining, such as finding a specific data value after reaching a specified instruction address, or reaching a second specified instruction address after reaching a first specified instruction address. The p-actions can include changing the sequential flow of instructions, i.e., vectoring to a new address, causing an interrupt, logging or counting an event, time stamping an event, initiating background operations such as direct memory access (DMA), caching prefetch operations, or the like.
In previous approaches, each p-event and its consequent p-action typically was treated uniquely and separately from other specific event-actions in order to solve some special problem. One of the many new contributions the architecture of the present invention provides is a generalized eventpoint mechanism. A requirement of the traditional sequential model of computation is that the processor efficiently handle the programming constructs that affect the sequential flow of instructions to be executed on the processor. In the prior art, one of these programming constructs is an auto-looping mechanism, which is found on many digital signal processors (DSPs). Auto-looping is employed to change the program flow for repetitive loops without the need for branch instructions, thereby improving the performance of programs that use loops frequently. Nested loops have also been supported in the prior art.
It has also been found imperative that a processor support facilities to debug a program. In the prior art, the capability of setting breakpoints on instructions, data, or addresses that cause a branch to a specified target address or cause an interrupt has been developed. The interrupt or debug branch directs the program flow to a special program that provides debug operations to aid the programmer in developing their software.
In another example, it has also been found imperative that a processor support facilities for initiating a DMA operation to occur in the background of normal program execution. In the past, the background DMA capability was typically initiated by specific DMA instructions or instructions specialized for DMA by nature of the side effect that they cause.
Consequently, auto-looping, background DMA operation, debug breakpoint capability, and other unique p-events and their consequent p-actions, represent approaches that have been considered separately in the prior art. The present invention generalizes these functions and provides additional unique capabilities that arise due to the generalization of the various p-events and p-actions in a common architecture thereby providing a common design and program approach to the development and use of all of these types of functions.
SUMMARY OF THE PRESENT INVENTION
The present invention addresses the need to provide a processor with a generalized p-event and p-action architecture which is scalable for use in a very long instruction word (VLIW) array processor, such as the ManArray processor. In one aspect of the invention, generalized p-event detection facilities are provided by use of a compare performed to discover if an instruction address, a data memory address, an instruction, a data value, arithmetic-condition flags, and/or other processor change of state eventpoint has occurred. In another aspect of this invention, generalized p-action facilities are provided to cause a change in the program flow by loading the program counter with a new instruction address, generating an interrupt, generating a log, counting the p-event, passing a parameter, etc. The generalized facilities may be advantageously defined in the eventpoint architecture as consisting of a control register and three eventpoint parameters: 1) a register to compare against, 2) a register containing a second compare parameter, vector address, or parameter to be passed, and 3) a count or mask register. Based upon this generalized eventpoint architecture, new capabilities are supported that extend beyond typical prior art capabilities. For example, auto-looping with capabilities to branch out of a nested auto-loop upon detection of a specified condition, background DMA facilities, and the ability to link a chain of p-events together for debug purposes, among others are all new capabilities easily obtained by use of this invention.
A more complete understanding of the present invention, as well as other features and advantages of the invention, will be apparent from the following Detailed Description and the accompanying drawings.
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Barry Edwin F.
Kurak, Jr. Charles W.
Marchand Patrick R.
Pechanek Gerald G.
Kim Kenneth S.
Priest & Goldstein,PLLC
PTS Corporation
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