Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2000-12-28
2003-12-16
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S025000, C710S107000, C710S110000, C710S305000, C710S308000, C710S311000, C710S313000
Reexamination Certificate
active
06665748
ABSTRACT:
FIELD OF THE INVENTION
The present invention can be used to add PCMCIA and ISA bus support to a low cost microprocessor (uP). More particularly, this invention provides a method of supporting PCMCIA devices with slow access times without sacrificing a large percentage of the microprocessoris data and address bus utilization. This can be accomplished by using the present invention in combination with one of the many low cost microprocessors that include a Direct Memory Access (DMA) Controller.
BACKGROUND OF THE INVENTION
The Personal Computer Memory Card International Association (PCMCIA) sets standards by which a CPU or host adapter interfaces with a peripheral over a specified interface. This PCMCIA interface is a full featured and versatile method of accessing a wide variety of peripheral devices. The interface provides for optional feature support, such as DMA, by the peripheral devices (PC Cards). Another important characteristic of the PCMCIA interface is that it is designed to interface to devices with great disparity in access speeds. When the CPU or host adapter initiates a transfer to or from the PCMCIA device, the PC Card can extend the access cycle to meet the needs of any slow hardware in the card. This allows PC Cards with different access times to all share the same bus interface. This introduces an important problem however, that when directly connected to a microprocessor's bus, slow PCMCIA devices can occupy a significant amount of the total available bus access time. The present invention will address this “bus utilization” problem.
The PCMCIA interface is unique in that in contains several control signals that are not found on PCI, ISA or other common PC CPU busses. To interface a CPU to a PCMICA card one of two options is typically followed. The first alternative is to use an external PCMCIA controller that is designed to interface to one of the common PC CPU bus architectures. There are several of these PCMCIA host adapter chips available, however they are not appropriate for low cost electronic designs because the host adapter adds significant cost, and like the PCMCIA card itself, it is not designed to interface to the simple bus control signals of low cost microprocessors.
The second commonly used method for accessing PCMCIA cards to is to use a highly integrated uP with a PCMCIA controller built in. This can be an attractive solution for small consumer electronic devices because these microprocessors are typically highly integrated devices with a wide range of peripherals (such as PCMCIA controllers, Ethernet controllers, Serial and Parallel ports) built into to the chip. This high degree of flexibility comes at a high price however, as the cost of these microprocessors are significantly higher then their equally powerful, but less versatile counterparts. Most of these highly integrated microprocessors, such as the Motorola PowerPC, suffer from the bus utilization problem discussed earlier. The PCMCIA card is attached to the same address and data bus as system memory and storage, so a slow PCMCIA device drastically reduces the time available to access the other system devices. The uP provides the specialized PCMCIA control signals, but does leaves the PCMCIA device connected to the system bus along with memory and other peripherals. There is at least one highly integrated uP, the AMD Elan, which does not suffer from the bus utilization problem. This full featured, and costly, alternative has a separate data and address bus for the PCMCIA cards is controls, and thereby removes the slow PCMCIA devices from the main system buses. This is an expensive solution to the bus utilization problem, especially for simple applications that do not take advantage of the wide variety of peripherals that drive up the cost of the processor.
The low cost microprocessors are a stark contrast to the highly integrated system on a chip devices just discussed. These can be fast and power processors, however they have limited built in peripherals. These processors have very basic bus and control signals which are sufficient to interface to simple memory peripherals like RAM and FLASH, however they are not able to interface directly to more sophisticated peripherals like Ethernet or PCMCIA host adapter chips. These peripheral adapters are designed to interface directly to a common PC bus (such as ISA or PCI) and not the simple bus of the low cost uP.
One capability which is common to many low cost microprocessors however, is their integration of a DMA Controller. A DMA Controller is typically used to copy data between a peripheral device and system memory. A DMA transfer is special because an external device can initiate each individual word transfer. In this manner the peripheral initiates the transfer by indicating to the uP that it is ready for a single read or write a access. One motivation for performing this kind of transfer is that the uP can continue to execute instructions and even make bus accesses while the bus is not being used to transfer data between to two devices in the DMA. Although this is an efficient way to transfer data between a peripheral and memory, it does not solve the bus utilization problem of slow PC Card devices. Because the device is still connected directly to the uP bus, the amount of time the bus is used by the PC Card remains the same.
What is needed is a low cost method to enhance a simple uP to include a PCMCIA interface without burdening the system bus with accesses to slow PC Card devices.
SUMMARY OF THE INVENTION
The present invention solves the above problems by the use of additional logic typically collected in either a Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC). The device functions as a Specialized PCMCIA Host Adapter (SPHA). The most fundamental operation of this logic is to interface between the simple bus of a low cost uP and the unique interface of PCMCIA devices. The PCMCIA control signals, as well as the data and address bus lines are completely isolated from the uP and only connected to the SPHA. The SPHA in turn is connected to the address, data and control lines of the uP.
The SPHA provides two methods modes to access the PC Card. The first method describes “Immediate Mode” accesses. In this mode the SPHA passes the PC Card address and data lines directly to those of the uP. This mode does not address the bus utilization problem since the PC Card signals have been connected directly to the uP. The SPHA still plays an important role in this mode however, as it is responsible for generating the PCMCIA control signals which are not native to the basic uP bus. When appropriate, the SPHA also provides the necessary Data Transmission Acknowledge (DTACK) signal to the uP to indicate that the access to the PC Card has completed. Immediate Mode access are appropriate for single or non-consecutive accesses to the PC Card.
The SPHA provides a second, more advanced, method of accessing the PC Card referred to as “DMA Mode.” This mode provides-highly efficient block (consecutive) transfers to or from the PC Card. This mode provides a solution to the bus utilization problem. The program code running on the uP sets up a DMA Mode transfer by configuring both the SPHA and the DMA controller on the uP. The SPHA then interacts with the uP DMA controller to accomplish a transfer between system memory and the PC Card.
When transferring a block of data from memory to the PC Card the SPHA will use a DMA control line to indicate that it is ready to read a word of memory from system RAM. Both system RAM and the SPHA have very low access times so the transfer between these two devices happens very quickly, with minimal utilization of the system bus. After the word is copied from system RAM, the SPHA then writes this word into the appropriate location in the PC Card. This transfer to the PC Card is done using signals that are completely isolated from the uP, so there is no impact of slow PC Card access times on the uP bus. Once the word has been written into the PC Card the process begins again until th
Slater James
Slater John T.
Wilkinson Scott
3Com Corporation
Perveen Rehana
Wagner , Murabito & Hao LLP
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