Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-12-26
2004-05-04
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S718000, C714S722000, C711S103000, C365S189070
Reexamination Certificate
active
06732306
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of testing semiconductor memories. More particularly, the present invention relates to a special programming mode for a semiconductor memory that uses hashing to help to optimize testing of a semiconductor memory.
BACKGROUND OF THE INVENTION
Over the years, different programming methods have been developed to program nonvolatile memory.
FIG. 1
shows prior art programming algorithm
10
for a prior art nonvolatile erasable programmable read-only memory (“EPROM”) that does not include on-chip program and erase automation circuitry. A microprocessor coupled to the EPROM executes programming algorithm
10
. The microprocessor sends a 100 microsecond programming pulse to the EPROM. The microprocessor then performs a word verification to determine if the word intended to be programmed into the EPROM has been successfully programmed. The algorithm terminates if 25 attempts fail to program a word. On the other hand, if the word was successfully programmed, then the algorithm repeats as it steps through each address.
FIG. 2
shows prior art programming algorithm
15
for a prior art early-generation flash nonvolatile memory. A microprocessor coupled to the prior art flash memory executes programming algorithm
15
. The flash memory is programmed on a word-by-word basis. The microprocessor writes a program command to the flash memory with a 10 microsecond time out. Thus, the programming operation takes 10 microseconds.
Following each programming operation, each word just programmed is verified by the microprocessor. The program verify operation is initiated by the microprocessor writing a program verify command into a command register of the flash memory. The program verify operation stages the flash memory for verification of the word last programmed. The flash memory applies an internally-generated margin voltage to the word. The microprocessor then performs a read cycle to output the word from the flash memory to the microprocessor. The microprocessor then compares the data word read from the flash memory to the data word that the microprocessor intended to program into the flash memory. A successful comparison between the programmed word and the time data means that the word was successfully programmed. If the data was not successfully programmed, then the program and verify steps are repeated with a limit of 25 attempts to program the word.
FIG. 3
shows a prior art programming algorithm
18
for a later-generation prior art flash memory that includes on-chip program and erase automation circuitry. The on-chip program and erase automation circuitry includes a command user interface, a write state machine, a data comparator, and a status register.
The program algorithm
18
begins with the microprocessor coupled to the flash memory writing a program setup command (i.e., 40 Hexadecimal) to the command user interface of the flash memory followed by a second write operation that specifies the address and data. After successful receipt and interpretation of the requested program operation, the command user interface of the flash memory forwards a translated signal to the write state machine of the flash memory then takes over, controlling an internal program algorithm within the flash memory. In particular, the write state machine supervises internal program and verify circuits to perform the following tasks: (1) program pulse control, (2) pulse repetition control, (3) time-out control, (4) program verification, and (5) status register update.
Assuming the memory location to be written to had been previously erased (i.e., stores all logical ones), in order to program the word in the flash memory array, the write state machine sends a programming pulse of a predetermined width to those memory cells that need to be programmed from a one to a zero.
Program verification then occurs in two steps. A margined-sensing read voltage is applied to the just-programmed cells. The resulting bit line currents are then fed individually to sense amplifiers, one sense amplifier per cell. The outputs of factory-set program reference circuits, adjusted to V
tp
(i.e., the program threshold voltage), are also fed into the respective sense amplifiers. The outputs of the sense amplifiers are then routed into a data comparator for collation. This collation compares the outputs of the sense amplifiers to the contents of a data register.
The data comparator reports the results of its collation to the write state machine, which in turn determines if pulse repetition is required. If the program verification operation shows that one or more cells need to be reprogrammed, the above program and program verification steps are repeated until either all the cells are verified as successfully programmed or a time-out occurs. When pulse repetition ends, the write state machine sends a signal to update the status register.
Bit seven of the status register (i.e., SR.7) is set to zero when the write state machine is busy. Bit seven of the status register is set to one when the write state machine is done (such as when programming ends) and is ready to perform the next operation. If bit four of the status register (i.e., SR.4) is set to one, that indicates that an error occurred in programming the word.
If the address at which the data word was programmed is not the last address, then the external microprocessor increments the address and repeats the above operations. In other words, the microprocessor sends the memory a 40 Hex program setup command followed by a write operation that specifies the incremented address and the associated data word. The memory programs the data word, performs internal program verification, and updates the status registers. The above process is repeated until all the data words are programmed.
Although prior art on-chip program verification is generally advantageous because the external microprocessor is freed to do other tasks, on-chip program verification has some disadvantages. With on-chip program verification, voltages are continuously being slewed from low to high levels and vice-versa, which generally lengthens programming times. Moreover, voltage and timing settings for the program and program verification operations are often chosen to handle worst case conditions, which also generally lengthens programming times. Furthermore, a program command precedes each data word to be programmed, further increasing programming times for long strings of data words.
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Dover Lance W.
Hasbun Robert N.
Reaves William T.
Ruby Paul D.
Blakely , Sokoloff, Taylor & Zafman LLP
De'cady Albert
Gandhi Dipakkumar
Intel Corporation
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