Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of...
Reexamination Certificate
2003-01-24
2004-11-23
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
C438S681000, C118S715000
Reexamination Certificate
active
06821910
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to processes which are used to deposit thin films of materials by processes such as chemical vapor deposition (CVD), in which chemically reactive gaseous species are introduced into the processing environment under controlled conditions of temperatures, gas flow and pressure, and in some cases additional plasma or optical excitation to cause the deposition of desired materials in thin film form on a substrate surface such as a semiconductor wafer. The deposition occurs because of chemical reactions between the gaseous species, usually involving reactions on the surface where deposition is desired, but sometimes involving reactions which occur in the gas phase and lead to formation of new species which then deposit on the surface.
BACKGROUND OF THE INVENTION
CVD is a widely used unit operation in the semiconductor manufacturing industry for thin film device production. The continuing reduction of device feature size and the development of new microelectronic devices have increased the demand for new electronic materials which meet specific materials performance objectives. Common modes of operation include (1) thermal CVD, in which the reaction requires only thermal energy (heating) to proceed, (2) plasma CVD, where a plasma discharge in the gas phase promotes the deposition reaction, and (3) others such as photo-CVD, where the deposition reaction is stimulated by optical excitation. To obtain the desired properties in the deposited thin films of metal, insulator, or semiconductor materials, various combinations of gases and process parameters are required. While selecting these optimal combinations has long been a challenge, to meet the demands of feature size reduction and device performance, the challenge is even greater today as fundamentally new and more complex materials and CVD chemistries are required, both for active devices (e.g., high dielectric constant insulators for FET gates) and for advanced interconnections (including low dielectric constant insulators, copper metallurgy, and metal nitride diffusion barrier layers).
Competitive manufacturing of semiconductors imposes a major additional requirement on CVD processes in the form of manufacturing performance. Silicon wafer sizes are being increased from eight inches to twelve inches diameter in order to reduce the cost per chip, where chips are of order 1 cm
2
area each. This increase in wafer size means more than twice the number of chips are now produced per wafer processed. However, the properties of each chip on the wafer must be virtually identical, requiring each process to exhibit uniformity of its metrics across the wafer, e.g., to within 1%. Furthermore, the processing rates must be sufficiently high for rapid deposition and high throughput, as needed for cost minimization. Similar considerations apply in other CVD application areas, such as plasma CVD processing of flat panel displays. Besides plasma-enhanced CVD, plasma etch processes are widely exploited for etching of materials, especially directional etching as needed for the fabrication of submicron device and interconnect structures and present similar problems and consideration.
The various CVD and plasma process modes, described above, have been and are regularly employed in the manufacturing of advanced products. Where the products entail a large area, as in the case of large silicon wafers for semiconductor chips or large glass panels for flat panel displays, the materials performance requirements must be met across a wide spatial extent (8-15 inches) and specified spatial uniformity demands for manufacturing performance.
The conventional approach to achieving simultaneous materials performance and across-wafer uniformity for manufacturing is to design the CVD equipment for single-wafer processing so that gas fluxes impinge as uniformly as possible across the wafer. To attempt to obtain maximum uniformity of gas impingement, some or all of the gases are delivered to the wafer through a showerhead, consisting of a flat plate parallel to and near the wafer surface. The gas passes through a high density of uniformly spaced small holes in the showerhead, thus distributing the gas flow as uniformly as possible across a large diameter wafer. In addition, reactor design components—including chamber, wafer position (and rotation), pumping, heating, and gas inlet—are constructed to attempt to maximize uniformity in terms of 2-D cylindrical symmetry about the wafer.
Various showerhead designs have been developed to attempt to generate uniform gas flow patterns over the wafer surface or for uniform film deposition. The requirement of across-wafer process uniformity has been a major driving force for the industry trend to single-wafer processing and the delivery of gases through a showerhead in relatively close proximity to the wafer surface (from about 2 to 20 mm).
For plasma processing equipment, the power distribution means used to generate the plasma must also be designed to attempt to produce uniform effects across the wafer. Much of plasma processing equipment today is single-wafer. For reactive ion etching and for plasma CVD, gas is introduced through a showerhead parallel to and near the wafer surface. This showerhead serves to distribute the reactant gas species in a relatively uniform manner and also as a counterelectrode for the plasma discharge, with the wafer attached to the other electrode.
Known single-wafer CVD and plasma process equipment using showerhead gas delivery provides a reasonably high degree of symmetry to the process. However, because the gas is introduced as uniform flux but is pumped away at the edges of the wafer, the deposition symmetry is radial, so that nonuniformities are experienced primarily in the radial direction, e.g., thicker films result in the wafer center region relative to the edges. Because the deposition reaction consumes the impinging reactant species, the flow of gases radially across the wafer leads to radial nonuniformities, the extent of which depend on the particular chemical species in use.
A more flexible design to achieve increased radial uniformity for complex CVD chemistries involves a three-zone showerhead as disclosed in U.S. Pat. No. 5,453,124 to Moslehi et al. which has been used for tungsten CVD. In this system, gas is introduced from three independently controlled concentric annular rings, each of which features individual zone feed gas mass flow controllers with potential for real-time control of process gas flows to each annular segment. The center region is circular, while the outer two are doughnut-shaped. By changing the gas flows in one zone relative to another, one can attempt to alter radial profile of deposition rate.
In practice, this has seen limited use for depositing metal compound barrier layers, using a single feed gas and with manually switched flow conductance elements to shorten development cycle time for new process equipment. Although this design has been able to achieve some improved radial uniformity, it still presents significant drawbacks in that it presents a single fixed rather than modular construction, it does not provide for exhaust gas sampling through or real-time sensing in the showerhead, it only permits control of processed gas flows to fixed annular segments, and due to the fact that the gas is pumped away at the edges of the wafer, significant intersegment convective mixing occurs.
Other approaches to controlling process uniformity have been directed to attempting to control spatial distribution of process variables other than gas flow. In rapid thermal processing (RTP), wafers are heated rapidly to reaction temperatures and maintained at these temperatures briefly to accomplish annealing, thermal oxidation, or CVD. In RTP, the key issue is temperature uniformity, both during the reaction and during temperature ramp-up. To compensate for radial temperature nonuniformities during RTP (associated primarily with different heat loss rates at the wafer edge cf. its center), multizone lamp heating arrays have been empl
Adomaitis Raymond A.
Kidder, Jr. John N.
Rubloff Gary W.
Ghyka Alexander
Liniak Berenato & White
University of Maryland College Park
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