Spacers used to form isolation trenches with improved corners

Details Spacers used to form isolation trenches with improved corners Spacers used to form isolation trenches with improved corners

1992-12-10

1995-07-18

Fourson, George

Metal treatment

Barrier layer stock material, p-n type

With non-semiconductive coating thereon

257506, H01L 4900

Patent

active

054337941

ABSTRACT:
A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.

REFERENCES:
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4549927 (1985-10-01), Goth et al.
patent: 4571819 (1986-02-01), Rogers et al.
patent: 4582565 (1986-04-01), Kawakatsu
patent: 4661832 (1987-04-01), Lechaton et al.
patent: 4729006 (1988-03-01), Dally et al.
patent: 4740480 (1988-04-01), Ooka
patent: 4952524 (1990-08-01), Lee et al.
patent: 4985368 (1991-01-01), Ishii et al.
patent: 5059550 (1991-10-01), Tateoka et al.
patent: 5168076 (1992-12-01), Gudoltino et al.
"A New Three-Dimensional MOSFET Gate-Induced Drain Leakage Effect In Narrow Deep Submicron Devices", Geissler et al., IBM General Technology Division, 1991 IEEE, pp. 839-842.
"A Simplified Box (Buried-Oxide) Isolation Technology For Megabit Dynamic Memories", Shibata et al., Toshiba Research and Development Center, 1983 IEEE, pp. 27-30.
"A Variable-Size Shallow Trench Isolation (STI) Technology With Diffused Sidewall Doping For Submicron CMOS" Davari et al., IBM T. J. Watson Res. Center, 1988 IEEE, pp. 92-95.
"A New Planarization Technique, Using A Combination Of RIE And Chemical Mechanical Polish (CMP)", Davari et al., IBM Research, T. J. Watson Res. Center, 1989 IEEE, pp. 61-64.
"The Inverse-Narrow-Width Effect", Lex A. Akers, IEEE Electron Device Letters, vol. EDL-7, No. 7, Jul. 1986, pp. 419-421.
"Trench Isolation With Boron Implanted Side-Walls For Controlling Narrow Width Effect Of N-MOS Threshold Voltages", Fuse et al., Semiconductor Research Center, Matsushita Electric Industrial Co., V1-2, pp. 58-59 (date unknown).
"A Practical Trench Isolation Technology With A Novel Planarization Process", Fuse et al., Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd 3-15, 1987 IEEE, pp. 732-735.
IBM Tech. Disc. Bull., vol. 31, No. 7, pp. 178-179, Dec. 1988.

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