Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-06-03
2001-10-16
Fabmry, Wael (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S639000
Reexamination Certificate
active
06303489
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication, and in particular, dual damascene processing of conductive lines and vias.
2. Background
An integrated circuit is formed by successive fabrication steps of depositing insulative material, forming grooves in the insulative material according to a specific pattern, and filling those grooves with conductive material. The filled material forms conductive lines and vias. Successive layers of conductive material form the integrated circuit elements and their interconnections. This fabrication process is known as damascene processing.
Dual damascene is a process whereby multilevel grooves are formed creating both conductive line openings and via openings to be filled in one process step with conductive material. An insulative material is coated with a resist layer, also known as a photomask, which is exposed to a mask with an image pattern of via openings. The upper half of the insulative material is etched. The photomask is then removed. The insulative material is again coated with a resist layer, which is exposed to a second mask with an image pattern of conductive lines. The insulative material is etched again. Grooves for the conductive lines are formed in the upper half of the insulative material and the already existing via openings are simultaneously etched in the lower half of the insulative material. The grooves are then filled with a conductive material, forming vias and conductive lines.
Dual damascene processing allows simultaneous filling of conductive lines and vias eliminating process steps. However, when using dual damascene processing with soft materials as the insulative material, such as a polymer material, the edges of the via openings are poorly defined due to the dual etchings.
SUMMARY OF THE INVENTION
A method of integrated circuit fabrication using soft materials for the insulative layer, such as a polymer material, utilizing dual damascene processing is disclosed. A spacer layer is utilized to improve the vertical edges of conductive lines and vias in an insulative material. Hard mask layers deposited on insulative material layers are utilized to improve the definition of horizontal edges of conductive lines and vias in the insulative material.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.
REFERENCES:
patent: 4832789 (1989-05-01), Cochran et al.
patent: 5614765 (1997-03-01), Avanzino et al.
patent: 5635423 (1997-06-01), Huang et al.
patent: 5686354 (1997-11-01), Avanzino et al.
patent: 5686357 (1997-11-01), Howard
patent: 5705430 (1998-01-01), Avanzino et al.
patent: 5795823 (1998-08-01), Avanzino et al.
patent: 5904565 (1999-05-01), Nguyen et al.
patent: 5916823 (1999-06-01), Lou et al.
patent: 5940731 (1999-08-01), Wu
patent: 5960318 (1999-09-01), Peschke et al.
patent: 5981376 (1999-11-01), Komatsu et al.
patent: 5985762 (1999-11-01), Geffken et al.
Advanced Micro Devices , Inc.
Eaton Kurt
Fabmry Wael
Williams Morgan & Amerson
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