Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1997-02-14
1998-09-08
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711109, 395872, 365 78, 36518912, 365220, G06F 1316, G06F 1202
Patent
active
058060847
ABSTRACT:
A space saving method and floor plan for fabricating an integrated circuit comprising a high density buffer memory. The method and floor plan allow for a significant reduction in the physical area required for a buffer memory of any given size that is fabricated on integrated circuit. Buffer applications wherein random access to the buffered data is not required use a CMOS dynamic serial memory with p-channel devices supplied with a voltage less positive than the voltage supplied to their respective n-wells. In a particular embodiment, three memory stages are used in a cascaded fashion. The first and third memory stages store data on a parallel basis, while the second memory stage stores data on a serial basis. The second memory stage call be fabricated using much less chip area per bit than the first and third memory stages. Significant area reduction is achieved because the second memory stage eliminates addressing overhead associated with conventional high-density memory schemes, and low voltage power supplies permit relaxation of latch-up prevention layout rules.
REFERENCES:
patent: 3491341 (1970-01-01), Alaimo
patent: 3736568 (1973-05-01), Snook
patent: 3859640 (1975-01-01), Eberlein et al.
patent: 3968478 (1976-07-01), Mensch, Jr.
patent: 4084154 (1978-04-01), Panigrahi
patent: 4393464 (1983-07-01), Knapp et al.
patent: 4513392 (1985-04-01), Shenk
patent: 5600815 (1997-02-01), Lin et al.
Hodges et al., Analysis and Design of Digital Integrated Circuits, McGraw-Hill, Inc., 1988, pp. 364-365.
Mano, Computer Engineering Hardware Design, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1988, pp. 72-73, 156-158, and 384-385.
Microsoft Press: Computer Dictionary, Microsoft Press, 1994, 354-355.
Rosenberg, Dictionary of Computers, Information Processing, and Telecommunications, John Wiley & Sons, 1987, pp. 565-567.
Walker, "Serial Interface Buffers Parallel Data, " EDN Electrical Design News, vol. 32, No. 12, Jun. 11, 1987, pp. 208 and 210.
Yeung et al., "A 300MHz Bipolar-CMOS Video Shift Register with FIFO," IEEE International Solid State Circuits Conference, Feb. 25, 1987, pp. 56, 57, and 338.
Lin Chong Ming
Werner Raymond J.
Bragdon Reginald G.
Chan Eddie P.
Seiko Epson Corporation
LandOfFree
Space saving method and floor plan for fabricating an integrated does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Space saving method and floor plan for fabricating an integrated, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Space saving method and floor plan for fabricating an integrated will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1296448