Static information storage and retrieval – Read/write circuit – Differential sensing
Patent
1997-09-26
1999-03-02
Nelms, David
Static information storage and retrieval
Read/write circuit
Differential sensing
365208, 365 51, 365 63, 36523006, G11C 702, G11C 800, G11C 502, G11C 506
Patent
active
058779949
ABSTRACT:
A semiconductor memory having a plurality of memory cells arranged in rows and columns includes a bank of sense amplifiers disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier in the bank disposed in a sense amplifier region between a pair of complementary bit lines of an associated column. An MDQ switch being located in a sense amplifier region occupying a corresponding row-wise space to the at least one driver to provide space efficient placement thereof.
REFERENCES:
patent: 5546349 (1996-08-01), Watanabe et al.
patent: 5636158 (1997-06-01), Kato et al.
"A 286mm.sup.2 256Mb DRAM with X32 Both-Ends DQ", by Watanabe et al., IEEE Journal of Solid-State Circuits, vol. 31, No. 4, Apr. 1996, pp. 567-574.
Kirihata Toshiaki
Mueller Gerhard
Braden Stanton C.
International Business Machines - Corporation
Nelms David
Phan Trong
Siemens Aktiengesellschaft
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