Space-efficient layout method to reduce the effect of substrate

Details Space-efficient layout method to reduce the effect of substrate Space-efficient layout method to reduce the effect of substrate

1999-05-06

2000-08-15

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257301, 257304, 257306, 257311, H01L 27108

Patent

active

061040541

ABSTRACT:
A method for reducing the parasitic capacitance and capacitive coupling of nodes (106) in a dielectrically isolated integrated circuit (100) using layout changes. A separate area of floating silicon (110) is created adjacent two or more dielectrically isolated nodes (106). The two or more nodes (106) are chosen that "slew together" (i.e., nodes that are required to change by the same voltage at the same time). The area of floating silicon (110) is created by placing an additional trench (112) around both of the dielectrically isolated nodes (106).

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