Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2006-10-24
2006-10-24
Peyton, Tammara (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S005000, C710S036000, C710S052000, C375S316000, C375S354000
Reexamination Certificate
active
07127536
ABSTRACT:
A source-synchronous data receiver includes a storage device for sequentially storing data received from a data source, a data output device for sequentially outputting the data that is stored in the storage device, and a control for controlling the data output device, so that the data output device makes available particular data previously stored by the data storage device a programmable predetermined number of clock states after data is called for, e.g., a read command to the data source is initiated.
REFERENCES:
patent: 4945548 (1990-07-01), Iannarone et al.
patent: 6529570 (2003-03-01), Miller et al.
patent: 2002/0154718 (2002-10-01), Fong et al.
patent: 2004/0047441 (2004-03-01), Gauthier et al.
patent: 1 150 450 (2001-10-01), None
patent: 1 150 451 (2001-10-01), None
Henrion Carson D.
Taylor Gary L.
Chen Alan S.
Hewlett--Packard Development Company, L.P.
Peyton Tammara
LandOfFree
Source-synchronous receiver having a predetermined data... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Source-synchronous receiver having a predetermined data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Source-synchronous receiver having a predetermined data... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3647505