Source specific timing checks on synchronous elements using...

Details Source specific timing checks on synchronous elements using... Source specific timing checks on synchronous elements using...

2008-03-13

2010-11-23

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07840925

ABSTRACT:
A computer-implemented method of performing timing analysis upon a circuit design having synchronous circuit elements can include selecting a destination pin having a plurality of source pins, wherein each source pin of the plurality of source pins defines a data path to the destination pin. A slack of a selected path of the data paths to the destination pin can be determined. A timing adjustment of each of the plurality of source pins can be compared to the slack of the selected path, wherein each timing adjustment is determined using static timing analysis. A simulation node can be selectively included within the circuit design according to the comparison. The circuit design can be output.

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