Source side injection flash EEPROM memory cell with dielectric p

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257295, 257298, 257314, 257315, 257316, 257326, H01L 29788

Patent

active

060876956

ABSTRACT:
A semiconductor flash memory cell. A p-well is formed in a semiconductor substrate. A thin oxide layer is formed over the p-well and semiconductor substrate. A dielectric pillar extending up from the semiconductor substrate is formed to support a control gate. A select gate is formed that extends underneath the control gate to be between the control gate and the thin oxide layer. Next, a floating gate is formed to extend underneath the control gate to be between the control gate and the thin oxide layer. A source region is formed in the p-well to be adjacent to the floating gate. Finally, a drain is formed in the p-well, the drain formed adjacent to the select gate.

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