Source follower using two pairs of NMOS and PMOS transistors

Details Source follower using two pairs of NMOS and PMOS transistors Source follower using two pairs of NMOS and PMOS transistors

1993-10-13

1995-11-21

Hudspeth, David R.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326 36, 326 50, H03K 190948

Patent

active

054690854

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a semiconductor device, and in particular to a high performance CMOS circuit.


BACKGROUND ART

Conventionally, source-follower circuits were widely used as circuits for the efficient driving of low impedance loads. Such a conventional circuit is depicted in FIG. 10. This diagram indicates a source-follower circuit comprising 1 NMOS transistor 1001 and a load resistance (R.sub.L) 1002; the drive load 1003 is assumed to be C.sub.out. If the resistance during the ON state of the NMOS transistor is assumed to be R.sub.ON, then V.sub.out is calculated according to the following formula: ##EQU1## Herein, R.sub.ON is a resistance determined by the gate source differential voltage V.sub.GS (=V.sub.in -V.sub.out). R.sub.L is set to a sufficiently high value, and when R.sub.L >>R.sub.ON, formula (1) is simplified to V.sub.out =V.sub.DD ; however, in actuality, when Vout approaches V.sub.in, and the state shown in the formula: the NMOS transistor changes to the OFF state, so that R.sub.ON rapidly reaches a high value. That is to say, the situation is as shown in the following formula: set equal to 0, V.sub.out will be equal to V.sub.in, and the transistor acts as a linear amplifier of voltage gain 1. In order to rapidly charge a large load capacitance C.sub.out, it is preferable to obtain a sufficiently large W/L of the transistor. (W indicates channel width, while L indicates channel length)
At this time, the gate capacitance of the MOS transistor is Cox.multidot.L.multidot.W, and increases in proportion to the product of L and W. (Cox indicates the capacitance with respect to a surface area unit of the gate.) However, the voltage placed on both ends of the gate oxide film is essentially 0, so that the charge stored in this gate capacitance is, in actuality, 0, and accordingly, the effective input capacitance of the circuit of FIG. 10 seen from V.sub.in is essentially 0. That is to say, even if a large load capacitance (low impedance load) is carried on the output side of the circuit of FIG. 10, only a very small capacitance is apparent from the input side (the V.sub.in side) (high input impedance), so that such a circuit type has been widely known as an impedance conversion circuit. Such a circuit is extremely convenient for driving a large capacitance.
The threshold value of the NMOS transistor is set to V.sub.T =0, and when a fixed positive voltage V.sub.in is inputted into the circuit of FIG. 10, a fixed potential output V.sub.out =V.sub.in is maintained.
When this done, a current /R.sub.L is consumed. In order to reduce this consumption current, R.sub.L must be increased. Here, if the input voltage changes from the positive fixed value V.sub.in to 0, then the change in V.sub.out at this time is approximately as shown in FIG. 11; it decreases at time constant R.sub.L .multidot.C.sub.out, and approaches 0. That is to say, the time period in which the output level conforms to the input and changes to the low potential side shortens in proportion to R.sub.L. That is to say, in order to increase the speed of the circuit, it is preferable that the R.sub.L be as small as possible.
However, when R.sub.L is reduced, as is clear from formula (2), the current value at the time at which the fixed voltage is maintained is increased, and the consumption current increases. Moreover, as can be understood from formula (1), the level of V.sub.out is lowered, and at R.sub.ON >>R.sub.L, V.sub.out is approximately equal to 0. That is to say, the effect of this is to reduce the voltage gain of the amplifier of FIG. 10 in a striking manner.
The present invention was created in order to solve the problems stated above; it has as an object thereof to provide a semiconductor device which makes possible almost zero steady state consumption power of the source-follower circuit, is moreover capable of being operated at high speed, and is further accompanied by no reduction at all in voltage gain.


DISCLOSURE OF THE INVENTION

The present invention discloses a semiconductor dev

REFERENCES:
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patent: 5206544 (1993-04-01), Chen et al.
patent: 5258657 (1993-11-01), Shibata et al.

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