Electrical computers and digital data processing systems: input/ – Intrasystem connection
Patent
1998-06-02
2000-12-05
Sheikh, Ayaz R.
Electrical computers and digital data processing systems: input/
Intrasystem connection
710 1, 710 2, 710 4, 710 5, 710 25, 710110, 710118, 710119, 710126, 710127, 710129, 712 31, 712 33, 712 41, G06F 1300
Patent
active
061579718
ABSTRACT:
A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when additional time is needed to participate in the data transfer. If either the source module, destination module or both modules require more time, the bus master, in response to an active stretch bus access signal or signals for the module or modules, automatically extends the bus access cycle until all modules requiring additional time signal over the internal communication bus that they are ready to proceed with the data transfer. Consequently, the source module, destination module, or both modules can re-time a bus access cycle to accommodate the characteristics of that particular module. When the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus. In response to the active signal on the address increment disable line, the bus master inhibits changing the address for the duration of the data transfer. The module also drives an active signal on a expansion address off boundary line in the control bus when an internal expansion address of the module is not aligned with a natural boundary of a data bus of the internal communication bus to allow the bus master to adjust the width of the data transfer.
REFERENCES:
patent: 4558429 (1985-12-01), Barlow et al.
patent: 5398244 (1995-03-01), Mathews et al.
patent: 5506995 (1996-04-01), Yoshimoto et al.
patent: 5544334 (1996-08-01), Noll
patent: 5559750 (1996-09-01), Dosaka et al.
patent: 5659690 (1997-08-01), Stuber et al.
patent: 5822550 (1998-10-01), Mihaupt et al.
Adaptec, Inc.
Gunnison Forrest
Jean Frantz Blanchard
Sheikh Ayaz R.
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