Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-05-18
2003-06-03
Nguyen, T. V. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S138000, C711S139000, C711S144000, C711S145000, C711S170000, C711S173000
Reexamination Certificate
active
06574708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of caches and, more particularly, to allocation of space in caches.
2. Description of the Related Art
Caches are used frequently in systems to reduce the memory access latency. Typically, at any given time, caches store the most recently accessed data. For each access, the cache determines whether or not the accessed data is currently stored in the cache. If the data is stored in the cache (a cache “hit”), the cache responds to the access (updating the stored data if the access is a write, or providing the stored data if the data is a read). If the data is not stored in the cache (a cache “miss”), the data is transferred to/from memory. Generally, the cache allocates storage for the data if the access is a read. In some cases, the cache also allocates storage for the data if the access is a write.
Since the cache is finite, the allocation of storage for data which misses the cache frequently causes data currently stored in the cache to be replaced (referred to as “evicting” the stored data). If the evicted data is modified with respect to the corresponding copy of the data in memory, the cache writes the data back to the memory. Otherwise, the cache may simply overwrite the evicted data in the cache with the new data. Unfortunately, if the evicted data is accessed again at a later time, the evicted data will experience the longer memory latency instead of the shorter cache latency.
SUMMARY OF THE INVENTION
An apparatus including a cache is described. The cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache block storage location to store the cache block addressed by the access or does not allocate a cache block storage location in response to the cache allocate indication. In one implementation, the cache is coupled to an interconnect with one or more agents. In such an implementation, the cache accesses may be performed in response to transactions on the interconnect, and the transactions include the cache allocate indication. Thus, the source of a cache access specifies whether or not to allocate a cache block storage location in response to a miss by the cache access. The source may use a variety of mechanisms for generating the cache allocate indication. Cache allocation may be controlled on a finer grain level than if the cache allocated cache blocks in response to each cache miss. Cache pollution may be reduced.
Broadly speaking, a system is contemplated. The system comprises an agent configured to initiate a transaction addressing a first cache block and a cache coupled to receive the transaction. The cache includes a plurality of cache block storage locations for storing cache blocks. The agent is configured to transmit a cache allocate indication in the transaction, which indicates whether or not the cache is to allocate one of the plurality of cache block storage locations to store the first cache block if the transaction is a miss in the cache. If the transaction is a miss, the cache is configured to selectively allocate one of the plurality of cache block storage locations to store the first cache block responsive to the cache allocate indication.
Additionally, an apparatus is contemplated. The apparatus comprises a first circuit configured to generate a request for a transaction addressing a first cache block on an interconnect. The first circuit is further configured to determine whether or not a cache on the interconnect is to allocate a cache block storage location to store the first cache block if the first cache block is a miss in the cache. A second circuit is configured to transmit the transaction on the interconnect, the transaction including a cache allocate indication indicating whether or not a cache on the interconnect is to allocate a cache block storage location to store the first cache block if the first cache block is a miss in the cache.
Moreover, a cache is contemplated. The cache comprises a cache memory including a plurality of cache block storage locations and a control circuit coupled to receive a cache allocate indication corresponding to an access. The control circuit is configured to selectively allocate one of the plurality of cache block storage locations to store a first cache block addressed by the access, if the access misses in the cache, responsive to the cache allocate indication.
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Hayter Mark D.
Rowlands Joseph B.
Broadcom Corporation
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Nguyen T. V.
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