Source bus formation for a flash memory using silicide

Details Source bus formation for a flash memory using silicide Source bus formation for a flash memory using silicide

2000-08-08

2003-06-17

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

C438S211000, C438S221000, C438S257000, C438S264000, C438S262000, C438S294000, C438S524000, C438S533000, C438S593000, C438S594000, C438S430000, C438S445000, C438S453000, C438S682000

Reexamination Certificate

active

06579778

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a memory device on a semiconductor substrate. The present invention has particular applicability in manufacturing nonvolatile semiconductor memory devices having a source bus.
BACKGROUND ART
Conventional nonvolatile semiconductor memories, such as flash electrically erasable programmable read only memories (flash EEPROMs), typically comprise a floating gate memory cell, which includes a source region, a drain region and a channel region formed in a semiconductor substrate, and a floating gate formed above the substrate between the channel region and a control gate. A voltage differential is created in the cell when a high voltage is applied to the control gate while the channel region is kept at a low voltage, causing injection of electrons from the channel region into the floating gate, as by tunneling, thereby charging the floating gate. This movement of electrons is referred to as programming, and the high voltage (i.e., about 18 volts) applied to the control gate is known as program voltage.
FIG. 1
depicts a typical floating gate memory cell
120
, which includes source/drain regions
220
and channel region
230
formed in substrate
210
, such as by implantation of impurities, tunnel oxide
240
of about 95 Å, polysilicon floating gate
250
, dielectric layer
260
and polysilicon control gate
270
.
A typical architecture for a flash memory system includes several strings of floating gate memory transistors (or “memory cells”)
120
which form an array or “memory core”. A “source line” connects the sources of the strings. Peripheral devices, such as power transistors (not shown) supply voltages of up to 23 volts for programming and other functions of the memory system. The flash memory system described above is typically manufactured on semiconductor substrate
210
as illustrated in
FIGS. 1
,
2
,
3
A and
3
B. Initially, as depicted in
FIG. 3A
, field isolation regions
310
,
330
are formed, as by local oxidation of silicon (LOCOS), for the memory core and for peripheral circuitry, which will be formed in areas
321
. As shown in
FIG. 2
, the core field oxide regions
310
are typically formed as parallel rows separated by channel areas
320
. Source/drain regions S, D and channel regions (not shown) are thereafter formed in substrate
210
by implantation of impurities, followed by tunnel oxide layer
240
of the core memory cells and gate oxide layer of the peripheral devices (not shown), as by thermal oxidation. A first layer of polysilicon (“the poly1 layer”), which, after a series of etching steps, will form the floating gates
250
of the memory cells
120
and the gates of the peripheral devices, is then deposited, as by low pressure chemical vapor deposition (LPCVD), masked and etched.
In subsequent processing steps (not shown), a dielectric layer (reference numeral
260
in
FIG. 1
) is deposited, masked and etched, followed by deposition of a second polysilicon layer (“the poly2 layer”), which is masked and etched to form control gates
270
/word lines WL (see FIGS.
1
and
2
). At the same time the poly2 layer is etched, the poly1 layer is further etched in the core memory cell area to complete formation of floating gates
250
.
Thereafter, the source line Vss Bus (see
FIG. 3B
) is formed by a “self aligned source” technique (SAS). Referring to
FIG. 3B
, which is a cross-sectional view taken through line A-A′ in
FIG. 2
, field oxide
310
between the sources S is etched away and impurities
330
are implanted in substrate
210
, such as arsenic or phosphorus by ion implantation, after masking, to form conductive line Vss Bus connecting sources S.
The current demands for miniaturization into the deep submicron range for increased circuit density require formation of device features with high precision and uniformity, including optimization of memory cell isolation and peripheral circuit isolation, to maintain the performance of the flash memory system. To improve isolation in flash memory systems, a type of isolation structure known as trench isolation is used, as depicted in
FIG. 4A
, wherein shallow trenches
410
are etched in the substrate
400
and an oxide liner
420
is thermally grown on the trench walls. Trench
410
is then refilled with an insulating material
430
. The resulting structure is referred to as a shallow trench isolation (STI) structure.
Disadvantageously, when the SAS technique is used with an STI isolation scheme to form Vss Bus, liner
420
and insulating material
430
are etched away, leaving severe topography due to the steepness of trench sidewalls
410
a
(see FIG.
4
B). Consequently, when impurities
440
are implanted during SAS formation, trench sidewalls
410
a
do not receive a sufficient amount of dopant (due to their shallow angle with respect to the incoming implanted ions) and therefore have high resistivity. As a result, the overall resistance of Vss Bus is higher than optimal, thus degrading the performance of the finished device.
There exists a need for a flash memory methodology enabling utilization of STI and formation of a Vss Bus without undesirable electrical characteristics, thereby improving device performance and reliability.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of manufacturing a flash memory with STI and a low-resistance Vss Bus.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The objects and advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises forming a memory core region on a semiconductor substrate as a plurality of substantially parallel, substantially rectangular rows of field oxide separated at a first portion of each row by a source region and at a second portion of each row by a channel region adjacent to the source region; forming a polysilicon floating gate above each channel region; etching to remove the first portion of each row and expose a portion of the substrate corresponding to the first portion; forming a protective oxide spacer on a sidewall of each floating gate, the protective spacers extending onto each source region; ion implanting impurities into the source regions and the exposed portions of the substrate corresponding to the first portion of each row to form a layer of the impurities; and forming a metal silicide layer on the source regions and the exposed portions of the substrate corresponding to the first portion of each row to form a continuous conductor.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.


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Chang et al, ULSI Technology, 1996,McGraw-Hill, pp. 394-39

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