Source-biased memory cell array

Details Source-biased memory cell array Source-biased memory cell array

2002-12-09

2004-06-01

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189090

Reexamination Certificate

active

06744659

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of field-effect transistor (FET) memories, and particularly to techniques for reducing sub-threshold leakage currents in FETs making up an array of memory cells.
2. Description of the Related Art
Semiconductor computer memories typically comprise a number of memory cells arranged into a row and column array. The cells can be arranged to provide various types of memories, such as random access memory (RAM) and read-only memory (ROM).
A conventional ROM having an exemplary 4 row by 4 column array of memory cells is shown in FIG.
1
. Each memory cell
10
comprises a single FET transistor. The gates of the FETs in a given row are connected to a respective ROW line, the drains of the FETs in a given column are connected to a respective BITLINE, and the sources of the FETs in the array are connected to ground. The FETs are programmed by some means so that each is either intact (programmed to a “0”) or not (programmed to a “1”). To read the state of each memory cell, the BITLINEs are typically pre-charged to a particular supply voltage. A memory cell is then read by enabling its ROW line and sensing the voltage of its BITLINE. If the FET being read is intact, it conducts current from its drain to its source and pulls down the BITLINE voltage. If not intact, the BITLINE voltage is unaffected. The BITLINE voltage is sensed to determine the state of a memory cell.
In practice, there may be extended periods during which none of the memory cells are being read. Even when a ROM is being read, there are generally only a relatively small subset of memory cells which are read at any given time. Thus, most or all of the intact FETs in the array. are commonly in their “off” or “stand-by” states; i.e., with their ROW lines at ground and their BITLINEs at the supply voltage. Unfortunately, under these conditions, each intact FET which is “off” exhibits some sub-threshold leakage current; i.e., current which is conducted from drain to source when the FET's gate voltage is less that its threshold voltage. This leakage current is typically on the order of hundreds of nanoamps per FET, and for a large array, the total leakage current can add up to hundreds of milliamps or more.
The use of modern generation CMOS technologies can further exacerbate this problem. To produce faster switching speeds, FET channel lengths are becoming shorter, gate oxide layers are becoming thinner, and threshold voltages are becoming lower. Though these smaller geometry transistors provide faster switching speeds and higher “on” currents, the ability to turn these transistors off becomes very difficult, and excessive leakage currents can result.
One approach used to reduce leakage current is the application of a substrate back-bias voltage. The back-bias voltage is applied to the FET's substrate, which has the effect of increasing the FET's threshold voltage. This does reduce the FET's “off” current, but—because the back-bias voltage is always present—also reduces the FET's “on” current, which is undesirable. It is possible to switch the back-bias on only during stand-by mode, but the time required to switch the back-bias on and off may be prohibitively long since it requires driving the entire substrate of the IC, which is a high capacitive load.
SUMMARY OF THE INVENTION
A memory cell array is presented which overcomes the problems noted above, providing reduced “off” state leakage current while having little to no impact on a cell's “on” current or switching speed.
The present invention is a memory cell array which employs “source-biasing”, wherein a bias voltage is applied to the source of one or more FETs contained within a memory cell to reduce its “off” state leakage current. The source-bias voltage is selectively switched between a small positive bias voltage for “off” FETs and ground for FETs which are “on”.
A memory cell array in accordance with the present invention comprises a plurality of FETs arranged into a row and column array. Each column has a respective common node, to which the sources of all the FETs in the column are connected. A plurality of source-bias circuits is connected to respective common nodes. Each source-bias circuit comprises a resistance connected between the common node and ground, and a switch connected across the resistance which, when closed, provides a low-resistance conductive path between the common node and ground. The switch is closed in response to a “read select” signal which is enabled whenever one of the FETs connected to the source-bias circuit's common node is read. When the “read select” signal is disabled, the resistance conducts the sub-threshold drain-source leakage currents of the FETs connected to the source-bias circuit's common node, and thereby produces a voltage at the common node which positively biases the sources of the FETs and thereby reduces their sub-threshold drain-source leakage currents.
The invention is applicable to a number of different FET-based memory types, including ROMs and RAMs.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.


REFERENCES:
patent: 4543500 (1985-09-01), McAlexander et al.
patent: 4754167 (1988-06-01), Conkle et al.
patent: 4982365 (1991-01-01), Ohtani et al.
patent: 5159571 (1992-10-01), Ito et al.
patent: 6088277 (2000-07-01), Kim et al.

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