Source and shadow wear-leveling method and apparatus

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

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Reexamination Certificate

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07818492

ABSTRACT:
A flash memory system includes flash memory organized into a plurality of blocks of pages for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address. The system further has a flash controller for communicating with a host and the flash memory and includes volatile memory for storing a source-shadow table of logical addresses identifying blocks addressable by the physical addresses. The source-shadow table has an address mapping table and a property value table. The property value table is used to store property values, each of which is associated with a block of a predetermined group of blocks and is indicative of the number of times a block has been written since the last erase operation performed thereon. The property values correspond to the logical addresses of the address mapping table, wherein a block having been written no more than two times is re-written to different areas of the flash memory without requiring an erase operation.

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patent: 2002/0013879 (2002-01-01), Han
patent: 2003/0156473 (2003-08-01), Sinclair et al.
patent: 2004/0210706 (2004-10-01), In et al.
patent: 2005/0160218 (2005-07-01), See et al.
patent: 2007/0276988 (2007-11-01), Luo et al.

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