Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2006-04-18
2006-04-18
Guerrero, Maria F. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S585000, C438S586000, C438S157000, C438S671000
Reexamination Certificate
active
07029959
ABSTRACT:
A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include depositing an organic anti-reflective coating on the gate material and forming a gate mask on the organic anti-reflective coating. The organic anti-reflective coating around the gate mask may be removed, and the gate material around the gate mask may be removed to define a gate.
REFERENCES:
patent: 5965461 (1999-10-01), Yang et al.
patent: 6252284 (2001-06-01), Muller et al.
patent: 6362111 (2002-03-01), Laaksonen et al.
patent: 6379872 (2002-04-01), Hineman et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6448165 (2002-09-01), Yu et al.
patent: 6458662 (2002-10-01), Yu
patent: 6458680 (2002-10-01), Chung et al.
patent: 6537906 (2003-03-01), Mori
patent: 6583469 (2003-06-01), Fried et al.
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6630407 (2003-10-01), Keil et al.
patent: 6686231 (2004-02-01), Ahmed et al.
patent: 6794230 (2004-09-01), Huang et al.
patent: 6815268 (2004-11-01), Yu et al.
Digh Hisamoto et al.: “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al.: “Sub-20nm CMOS Fin FET Technologies,” 0-7803-5410-9/99 IEEE, Mar. 2001, 4 pages.
Xuejue Huang et al.: “Sub-50 nm P-Channel Fin FET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Yang-Kyu Choi et al.: “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Xuejue Huang et al.: “Sub 50-nm FinFET: PMOS,” 0-7803-7050-3/01 IEEE, Sep. 1999 4 pages.
Co-pending U.S. Appl. No. 10/301,732, filed Nov. 22, 2002, entitled “Method for Forming a Gate in a FINFET Device,” 17 page specification, 12 pages of drawings.
Ahmed Shibly S.
Dakshina-Murhty Srikanteswara
Tabery Cyrus E.
Yang Chih-Yuh
Yu Bin
Guerrero Maria F.
Harrity & Snyder LLP
LandOfFree
Source and drain protection and stringer-free gate formation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Source and drain protection and stringer-free gate formation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Source and drain protection and stringer-free gate formation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3527600