SONOS memory device with optimized shallow trench isolation

Details SONOS memory device with optimized shallow trench isolation SONOS memory device with optimized shallow trench isolation

2011-04-12

2011-04-12

Garber, Charles (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S242000, C438S248000, C438S391000, C438S700000, C438S954000, C257SE29322, C257SE21209

Reexamination Certificate

active

07923363

ABSTRACT:
Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area, said non-volatile memory device comprising a cell stack of a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first insulating layer; the method comprising: —providing the substrate having the first semiconductor layer; —depositing the charge trapping layer; —depositing the electrically conductive layer; —patterning the cell stack to form at least two non-volatile memory cells, and —creating a shallow trench isolation in between said at least two non-volatile memory cells.

REFERENCES:
patent: 6677639 (2004-01-01), Lee et al.
patent: 2002/0019113 (2002-02-01), Chung
patent: 2003/0080370 (2003-05-01), Harari et al.
patent: 2004/0004233 (2004-01-01), Shum et al.
patent: 2004/0070034 (2004-04-01), Park et al.
patent: 2004/0180550 (2004-09-01), Jeng
patent: 2005/0127428 (2005-06-01), Mokhlesi et al.

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