Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-21
2002-12-24
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S324000, C257S410000
Reexamination Certificate
active
06498377
ABSTRACT:
DESCRIPTION OF THE INVENTION
1. Field of the Invention
This invention relates in general to a silicon-oxide-nitride-oxide-silicon (SONOS) semiconductor component and, more particularly, to a SONOS component in a nitride read only memory (NROM) semiconductor device.
2. Background of the Invention
FIG. 1
is a prior art nitride read only memory (NROM) device
10
. Referring to
FIG. 1
, the NROM device
10
includes a substrate
12
having an n-type source region
14
, an n-type drain region
16
, and a p-type channel region
18
formed therebetween. The NROM device
10
also includes an oxide-nitride-oxide (ONO) structure
28
formed over the channel region
18
and portions of the source
14
and drain
16
regions. The ONO structure
28
includes a first oxide layer
20
formed over the substrate
12
, a nitride layer
22
formed over the first oxide layer
20
, and a second oxide layer
24
formed over the nitride layer
22
. The NROM device
10
further includes a gate structure
26
formed over the second oxide layer
24
, and sidewall spacers (not shown) contiguous with at least the gate structure
26
.
The nitride layer
22
“stores” electrical charges by trapping electrons therein, and the thickness of the first and second oxide layers
20
,
24
should be sufficient to prevent leakage, i.e., direct tunneling of stored electrons under normal operating conditions. Erasing is accomplished using tunnel-enhanced hot hole injection, and programming is performed by channel hot electron injection. The NROM device
10
may store up to two physically separated bits, but only one bit may be programmed and stored at a time. U.S. Pat. No. 6,011,725, entitled “Two Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping,” by Boaz Eitan describes a non-volatile memory device based on an NROM cell for storing two bits of data, and is hereby incorporated by reference.
Because the nitride layer
22
is capable of storing charges independently, two bits of data may be written into the NROM device
10
. Referring again to
FIG. 1
, electrons are injected, during programming, into the nitride layer
22
at one of the injection points A and B, and stored in one of portions
22
-
1
and
22
-
2
, respectively, of the nitride layer
22
. The injection point A is located at the junction between the source region
14
and channel region
18
. The injection point B is located at the junction between the drain region
16
and channel region
18
. Both the source region
14
and drain region
16
encroach the area of the substrate
12
directly beneath the gate structure
26
because of diffusion of the n-type impurities. As a result, both of the injection points A and B are located underneath the gate structure
26
.
Because of the proximity between the portions
22
-
1
and
22
-
2
, interference, or cross-talk, between the stored two bits of data may prevent the stored data from being accurately read out. Thus, the locations for storing the electron charges are generally separated by as much distance as possible.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided a semiconductor memory device that includes a substrate having a source region, a drain region, and a channel region formed therebetween, a first oxide layer formed over the channel region, a nitride layer formed over the first oxide layer, a second oxide layer formed over the nitride layer, a gate structure formed over the second oxide layer, wherein a region in the substrate underneath the gate structure excludes one of the source and drain regions, and at least one sidewall spacer formed over the nitride layer and contiguous with the gate structure, wherein the at least one sidewall spacer has a dielectric constant value sufficient to form an inversion region in a substrate region underneath the sidewall spacer to connect the region beneath the sidewall spacer with the channel, source and drain regions, and wherein electron charges are stored in portions of the nitride layer underneath the at least one sidewall spacer.
In one aspect, the semiconductor device further includes at least one injection point for injecting electrons into the nitride layer, wherein the injection point is located at a junction between the channel region and one of the source and drain regions.
In another aspect, the injection point is located underneath the sidewall spacer.
In yet another aspect, the dielectric constant value is between approximately 25 and 30.
Also in accordance with the present invention, there is provided a over the channel region, a nitride layer formed over the first oxide layer, a second oxide layer formed over the nitride layer, a gate structure formed over the second oxide layer, wherein a region in the substrate underneath the gate structure excludes one of the source and drain regions, a plurality of sidewall spacers formed over the nitride layer and contiguous with the gate structure, and at least one injection point for injecting electrons into the nitride layer, wherein the injection point is located at a junction between the channel region and one of the source and drain regions, and wherein electron charges are stored in portions of the nitride layer underneath the sidewall spacers.
In one aspect, the injection point is located underneath one of the sidewall spacers.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 5473179 (1995-12-01), Hong
patent: 5966603 (1999-10-01), Eitan
patent: 6011725 (2000-01-01), Eitan
patent: 6166958 (2000-12-01), Naruke et al.
patent: 6291297 (2001-09-01), Chen
Lai Han Chao
Lin Hung-Sui
Lu Tao Cheng
Zous Nian Kai
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Macronix International Co. Ltd.
Wilson Allan R.
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