Solving constraint satisfiability problem for circuit designs

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C703S014000, C703S015000

Reexamination Certificate

active

07073143

ABSTRACT:
A method for generating a test vector for functional verification of circuits includes providing a representation of a circuit, where the representation includes a control logic component and a datapath logic component. The method also includes reading one or more vector generation targets, and performing word-level ATPG justification on the control logic component to obtain a control logic solution. The method further includes extracting one or more arithmetic functions for the datapath logic component based on the control logic solution, and solving the one or more arithmetic functions using a modular constraint solver. The modular constraint solver is based on a modular number system.

REFERENCES:
patent: 5276897 (1994-01-01), Stalmarck
patent: 5937183 (1999-08-01), Ashar et al.
patent: 6035107 (2000-03-01), Kuehlmann et al.
patent: 6038392 (2000-03-01), Ashar et al.
patent: 6292916 (2001-09-01), Abramovici et al.
patent: 6442732 (2002-08-01), Abramovici et al.
patent: 6975976 (2005-12-01), Casavant et al.
patent: 2005/0039077 (2005-02-01), Iyer
patent: 2005/0044055 (2005-02-01), Iyer
C-Y Huang et al., Assertion Checking By Combining Word-Level ATPG and Modular Arithmetic Constraint Solving Techniques, Proceedings of the 37thConference on Design Automation, pp. 118-123, Jun. 2000.
M. Ganai et al., Enhancing Simulation with BDDs and ATPG, Proceedings of the ACM/IEEE Conference on Design Automation, pp. 385-390, Jun. 1999.
R. Vemuri et al., Generation of Design Verification Tests from Behavioral VHDL Programs Using Path Enumeration and Constraint Programming, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 201-214, Jun. 1995.
Chang-Yang (Ric) Huang, et al.; “Using Word Level ATPG and Modular Arithmetic Constraint-Solving Techniques for Assertion Property Checking”; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, No. 3, Mar. 2001; pp. 381-391.
Farzan Fallah, et al.; “Functional Vector Generation for HDL models Using Linear Programming and 3-Satisfiability”; Proceedings of 1998 Design Automation Conference; Jun. 15-19, 1998; pp. 528-533.
Ranga Vemuri, et al.; “Generation of Design Verification Tests from Behavioral VHDL Programs Using Path Enumeration and Constraint Programming”; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; vol. 3, No. 2, Jun. 1995; pp. 201-214.
“Murphi Description Language and Automatic Verifier”; http://sprout.stanford.edu/dill/murphi.html; Nov. 7, 2001; pp. 1-6.
Kenneth L. McMillan; “Symbolic Model Checking”; Kluwer Academic Publishers; 1993.

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