Solventless, resistless direct dielectric patterning

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device

Reexamination Certificate

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C430S311000, C430S331000, C216S062000

Reexamination Certificate

active

06509138

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to methods of lithographic patterning using solvent-free compositions. The invention also relates to direct patterning without resists.
BACKGROUND OF THE INVENTION
Current lithographic processes employed by the microelectronics industry have significant environmental, safety and health (ESH) impacts. The fabrication of semiconductor devices uses photoresist to lithographically define features at every mask level. Advanced complementary metal oxide semiconductor (CMOS) and bipolar integrated circuit (IC) processes can require in excess of twenty-five mask levels. This large number of processing steps results in significant volumes of chemicals being consumed. Wet solutions are used for the application of the photoresist layer and during the development step. Thus, improved resist processing presents a clear need and an opportunity to reduce the ESH impact of microelectronics manufacturing. The present invention fulfills this and other needs.
SUMMARY OF THE INVENTION
One embodiment of the present invention relates to a process for lithographically patterning a material on a substrate comprising the steps of:
(a) depositing a radiation sensitive material on the substrate by chemical vapor deposition;
(b) selectively exposing the radiation sensitive material to radiation to form a pattern; and
(c) developing the pattern using a supercritical fluid (SCF) as a developer.
Another embodiment of the present invention relates to microstructures formed by the foregoing process.
Another embodiment of the present invention relates to a process for lithographically patterning a material on a substrate wherein after steps (a) and (b) above, the pattern is developed using a dry plasma etch.
Another embodiment of the present invention relates to a microelectronic structure comprising a substrate; and a patterned dielectric layer, wherein the patterned dielectric layer comprises at least one two-dimensional feature having a dimensional tolerance more precise than 7% of dimension of the two-dimensional feature.
These and other embodiments of the invention are discussed in further detail below.


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