Solid state three dimensional semiconductor memory array

Details Solid state three dimensional semiconductor memory array Solid state three dimensional semiconductor memory array

1982-06-03

1985-08-13

Popek, Joseph A.

Static information storage and retrieval

Interconnection arrangements

365 51, G11C 1700

Patent

active

045354243

ABSTRACT:
A memory circuit including several semiconductor substrates, each containing addressable memory elements, address receiving circuitry for receiving address signals and for providing data from the memory in response to the address signals, control circuitry for receiving control signals and for controlling the reading and writing of the memory elements, and interconnection circuitry including elevated portions of the semiconductor substrate connected to contact paths of the semiconductor substrate located above to provide electrical continuity between the addressable circuits of each semiconductor substrate and electrical continuity between the control circuits of each semiconductor substrate.

REFERENCES:
patent: 3704455 (1972-11-01), Scarbrough
R. A. Jarvela et al., "Stacked High-Density Multichip Module", IBM Technical Disclosure Bulletin, vol. 14, No. 10, Mar. 1972, pp. 2896-2897.

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