Solid state memory having a latch circuit

Details Solid state memory having a latch circuit Solid state memory having a latch circuit

1999-09-27

2000-12-05

Dinh, Son T.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518505, 36518507, G11C 800

Patent

active

061575909

ABSTRACT:
A solid state memory according to the present invention comprises a plurality of memory chips; a confirmation circuit to confirm an input address by comparing said input address to each address latched to a latch circuit; a common serial bus for transmitting commands, addresses and data between the memory chips and the confirmation circuit; and a printed circuit board on which the memory chips and the confirmation circuit are mounted.

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patent: 5568424 (1996-10-01), Cernea et al.
patent: 5592420 (1997-01-01), Cernea et al.
patent: 5621685 (1997-04-01), Cernea et al.
patent: 5809337 (1998-09-01), Hannah et al.
patent: 5838614 (1998-11-01), Estakhri et al.

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