Solid state imager

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S288000

Reexamination Certificate

active

06617625

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-191321, filed Jun. 26, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device structure of a pixel section of a solid state imager.
2. Description of the Related Art
FIG. 1
shows a circuit structure of a pixel section of a sense type solid state imager.
A pixel comprises a photodiode
21
for converting an optical signal to an electric signal (charge); a transfer gate (MOS transistor)
22
for transferring a charge of the photodiode
21
to a detection section (detection node) D; a reset gate (MOS transistor)
23
for resetting the charge (potential) in the detection section D; a sense gate (MOS transistor)
24
for amplifying the potential of the detection section D; and a select gate (MOS transistor)
25
for outputting a potential of a selected pixel.
A charge photoelectrically converted by the photodiode
21
and accumulated in a signal accumulation region over a predetermined time period is transferred to the detection section D via the transfer gate
22
. The charge transferred to the detection section D from the photodiode
21
varies the potential of the detection section D. The sense gate
24
amplifies the variation amount of the potential of the detection section D.
FIG. 2
is a plan view showing a prior-art device layout of a photodiode and a transfer gate.
FIG. 3
is a cross-sectional view taken along line III—III in
FIG. 2
, and
FIG. 4
is a cross-sectional view taken along line IV—IV in FIG.
2
.
A device isolation region
12
is provided on a p-type semiconductor substrate (or p-type well region)
11
. In this example, the device isolation region
12
is formed of a field oxide film by LOCOS (Local Oxidation of Silicon). Alternatively, the device isolation region
12
may be formed of an oxide film having, for example, an STI (Shallow Trench Isolation) structure.
A photodiode and a transfer gate are disposed in a device region surrounded by the device isolation region
12
.
In this example, the photodiode comprises the p-type semiconductor substrate
11
and an n-type signal accumulation region (impurity diffusion layer)
13
formed in the semiconductor substrate
11
. The transfer gate comprises the n-type signal accumulation region
13
and an n
+
detection section (detection node)
14
, both formed in the p-type semiconductor substrate
11
, and a gate electrode
15
formed on a channel region between the signal accumulation region
13
and detection section
14
.
The n-type signal accumulation region
13
functions as a cathode of the photodiode and also as a source of the transfer gate. The impurity density in the n-type signal accumulation region
13
is set at a lowest possible level in order to transfer all the charge accumulated by photoelectric conversion in the signal accumulation region
13
to the detection section
14
. The detection section
14
is connected to an amplifier circuit
17
(e.g. sense gate
24
in FIG.
1
).
In the above-described sense type solid state imager, the less the parasitic capacitance in the detection section
14
, the greater the signal potential that is obtained in the detection section
14
relative to a predetermined charge amount accumulated in the signal accumulation region
13
. In other words, the less the parasitic capacitance in the detection section
14
, the greater the photosensitivity of the image sensor.
It is thus desirable that the detection section
14
be designed with a smallest possible size in order to decrease the parasitic capacitance and to enhance the photosensitivity of the image sensor. On the other hand, it is important that the signal accumulation region
13
be designed with a greatest possible size in order to receive as much as possible light and to generate as much as possible charge by photoelectric conversion.
For these reasons, as shown in
FIG. 2
, the signal accumulation region
13
of the pixel section of the prior-art solid state imager has a large size, while the detection section
14
has a small size.
As is shown in
FIG. 2
, in the prior-art solid state imager, the size of the signal accumulation region
13
is increased as much as possible, and the size of the detection section
14
is decreased as much as possible.
The device region is surrounded by the device isolation region
12
, and the position and size of the device region are determined by the device isolation region
12
. In addition, in this example, the positions and sizes of the signal accumulation region
13
and detection section
14
are also determined by the device isolation region
12
. In short, the edge portions (except portions adjoining the channel region) of the signal accumulation region
13
and detection section
14
coincide with the edge portions of the device isolation region
12
.
However, the device region is formed of a semiconductor (e.g. silicon) whereas the device isolation region
12
is formed of an insulator (e.g. silicon oxide). The material of the device region and that of the device isolation region
12
are different and, as a matter of course, have different thermal expansion coefficients.
Consequently, when heat is applied in a step of forming the device isolation region
12
or in other steps, thermal stress may occur and crystal defects may be caused in the semiconductor layer (device region) near the device isolation region
12
. The crystal defects may lead to a leak current. Such a leak current varies the potential of, in particular, the detection section
14
. Thus, a pseudo signal is produced by the leak current, and the stable operation of the solid state imager cannot be ensured.
It is well known that in the photodiode as shown in
FIGS. 2-4
, a problem arises due to so-called KTC noise (K: Boltzmann's constant; T: absolute temperature; C: capacitance of photodiode). In order to prevent the KTC noise, a p
+
surface shield layer may advantageously be formed on the n-type signal accumulation region
13
so that the photodiode may have a buried structure.
Adopting the buried-type photodiode structure, the n-type signal accumulation region
13
with a low impurity density can be completely depleted and all the charge in the signal accumulation region
13
can be completely transferred to the detection section
14
. In brief, this structure is advantageous in inactivating a surface defective level of the signal accumulation region
13
, suppressing a leak current and reducing KTC noise.
The depletion potential of the buried-type photodiode is determined by a two-dimensional effect. Thus, the peripheral portion of the signal accumulation region
13
has a lower depletion potential than the central portion thereof. Accordingly, as the size of the photodiode (the size of the signal accumulation region
13
) decreases, the depletion potential for depleting the entirety of the signal accumulation region
13
becomes lower and all the charge may advantageously be transferred.
However, as mentioned above, the size of the signal accumulation region
13
cannot be decreased in order to receive as much as possible light and to generate as much as possible charge by photoelectric conversion.
The same trade-off problem arises with the channel width of the transfer gate (read gate). As is shown in
FIG. 2
, the channel width W
2
(equal to the dimension in one direction of the detection section
14
) of the transfer gate is normally set to be less than the size W
1
(i.e. the width in one direction) of the signal accumulation region
13
. The reason is that it is advantageous, as mentioned above, to minimize the size of the detection section
14
and to maximize the size of the signal accumulation region
13
, thereby to receive as much as possible light and to enhance the photosensitivity of the image sensor as high as possible.
If the channel width W
2
of the transfer gate is decreased, however, the wid

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Solid state imager does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Solid state imager, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Solid state imager will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3107250

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.