Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-14
2003-02-25
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S239000
Reexamination Certificate
active
06525355
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state image sensor, particularly relates to a solid-state image sensor provided with a divided photoelectric conversion part.
2. Description of the Related Art
Recently, a solid-state image sensor used for a digital camera, digital VTR and others has attracted a great deal of attention. Heretofore, a solid-state image sensor was roughly classified into a MOS type and a CCD type according to a system of a transport layer for transferring a photoelectrically converted signal charge.
Of these solid-state image sensors, particularly a CCD-type solid-state image sensor has been recently used for electronic equipment such as camera-integrated VTR, a digital camera and a facsimile and technical development for enhancing the characteristics is still currently made.
For one of such solid-state image sensors, there is a solid-state image sensor compatible with a CMOS manufacturing process (hereinafter called a CMOS sensor) (for example, refer to pages 120 to 125 in the July number in 1997 of the Nikkei Microdevice). This CMOS sensor can be operated by a single power source of 5 V or 3.3 V and is provided with characteristics that the power consumption is low, the CMOS sensor can be manufactured in a general CMOS manufacturing process, can be mounted in the identical chip together with a signal processing circuit and other peripheral circuits and is compatible with a CMOS manufacturing process.
FIGS. 10A and 11A
are sectional views respectively showing a basic cell (picture element) of a CMOS sensor.
FIG. 10B
is a potential phase diagram when signal charges are accumulated in a photoelectric conversion part and
FIG. 11B
is a potential phase diagram when signal charges in the photoelectric conversion part are reset.
As shown in
FIG. 10A
, the basic cell (picture element) of the CMOS sensor is provided with a P-type semiconductor substrate
301
, a P-type well layer
302
which is formed inside the P-type semiconductor substrate
301
and a part of which is exposed on the surface of the P-type semiconductor substrate
301
, P+-type semiconductor regions
303
and
323
formed on the P-type well layer
302
, exposed on the surface of the P-type semiconductor substrate
301
and functioning as an element separating region, an N+-type semiconductor region
306
surrounded by the P-type well layer
302
and the P+-type semiconductor region
303
and functioning as a photoelectric conversion part, an N+-type semiconductor region
305
surrounded by the P-type well layer
302
and the P+-type semiconductor region
323
and functioning as a drain of MOSFET for control
401
, the MOSFET for control
401
having a gate electrode located opposite to the exposed surface of the P-type well layer
302
exposed on the surface of the P-type semiconductor substrate
301
, first MOSFET
402
functioning as a source-follower amplifier and second MOSFET
403
functioning as a horizontal selecting switch.
The basic cell of the CMOS sensor is connected to an external circuit via the second MOSFET
403
.
The external circuit is composed of third load MOSFET
404
that receives the load of the source-follower amplifier, MOSFET for transferring dark output
405
, MOSFET for transferring light output
406
, a capacitor for accumulating dark output
407
connected to a source or a drain of the MOSFET for transferring dark output
405
and a capacitor for accumulating light output
408
connected to a source or a drain of the MOSFET for transferring light output
406
.
The second MOSFET
403
is connected to the third load MOSFET
404
. The MOSFET for transferring dark output
405
and the MOSFET for transferring light output
406
are connected to a node between the second MOSFET
403
and the third load MOSFET
404
.
The first MOSFET
402
, the second MOSFET
403
and the third load MOSFET
404
are connected in series between line sources VDD and VSS. The N+-type semiconductor region
306
is connected to a gate of the first MOSFET
402
.
The P+-type semiconductor regions
303
and
323
are grounded and the N+-type semiconductor region
305
is connected to a line source VDD.
The basic cell
450
shown as a picture element in
FIGS. 10 and 11
of the CMOS sensor is arranged in a matrix and a CMOS cell series is formed. Each basic cell
450
is connected to vertical registers (V-registers)
451
, horizontal registers (H-registers)
452
, the load transistor
404
and an output line
453
as shown in FIG.
12
A.
The load transistor
404
shown in
FIG. 12A
is identical to the load MOSFET
404
shown in
FIGS. 10 and 11
.
The output line
453
is connected to each MOSFET
405
,
406
and each capacitor
407
,
408
respectively shown in
FIGS. 10 and 11
via vertical selecting switch MOSFET
455
as a vertical selecting switch selected by the horizontal register
452
.
FIG. 12B
shows connection inside the basic cell (or a picture element) and the same reference number is allocated to a component corresponding to that in
FIGS. 10 and 11
. As shown in
FIG. 12B
, a control pulse &phgr;R is input to a gate of the MOSFET for control
401
, an address signal X is input to a gate of the second MOSFET
403
and the load transistor
404
and the output line
453
are connected to a source of the second MOSFET
403
.
Next, referring to
FIGS. 10 and 11
, a method of operating the CMOS sensor configured as described above will be described.
First, as shown in
FIG. 11
, the control pulse &phgr;R applied to the gate of the MOSFET for control
401
in reset time is set to the voltage of a high level and the N+-type semiconductor region
306
is reset to source voltage VDD.
As shown in
FIG. 10
after a reset is finished, the control pulse &phgr;R to the MOSFET for control
401
is set to the voltage of a low level.
In the N+-type semiconductor region
306
that functions as a photoelectric conversion part, kTC noise is caused by the reset, however, this can be removed by sampling and accumulating dark output before signal charges are transferred and eliminating difference between the dark output and light output.
In the succeeding accumulation period of signal charges, in the N+-type semiconductor region
306
that functions as a photoelectric conversion part, when an electron-hole pair is caused by incident light, electrons are accumulated in a depletion layer and the hole is discharged via the P-type well layer
302
. Grid-like hatching showing electric potential lower than the source voltage VDD shows that this region is not depleted.
The electric potential of the N+-type semiconductor region
306
that functions as a photoelectric conversion part varies according to the number of accumulated electrons. A photoelectric transfer characteristic satisfactory in linearity can be acquired by outputting the variation of the electric potential to the second MOSFET
403
via the source of the first MOSFET
402
by the source-follower operation of the first MOSFET
402
.
In the solid-state image sensor compatible with the CMOS manufacturing process, the electric potential of the N+-type semiconductor region
306
that functions as a photoelectric conversion part varies according to the number of accumulated electrons and the variation of the electric potential is output to the second MOSFET
403
via the source of the first MOSFET
402
by the source-follower operation of the first MOSFET
402
.
In this case, if the quantity of signal charges is Q, the parasitic capacity of the N+-type semiconductor region
306
that functions as a photoelectric conversion part is C and output voltage is V, V=Q/C.
FIG. 13
shows relation among the quantity of incident light, electric potential and output voltage.
However, as shown in
FIG. 10
, as a photoelectric conversion part is formed by the N+-type semiconductor region
306
in the solid-state image sensor compatible with the CMOS manufacturing process, there is a defect that the parasitic capacity C of the ph
Furumiya Masayuki
Nakashiba Yasutaka
Hayes & Soloway P.C.
Munson Gene M.
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