Solid state disk drive address generator with multiplier circuit

Details Solid state disk drive address generator with multiplier circuit Solid state disk drive address generator with multiplier circuit

1996-05-02

2000-03-07

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Incrementing, decrementing, or shifting circuitry

711217, 711218, 711220, G06F 1200

Patent

active

060353848

ABSTRACT:
An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a block size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

REFERENCES:
patent: 5070474 (1991-12-01), Tuma et al.
patent: 5088031 (1992-02-01), Takasaki et al.
patent: 5179662 (1993-01-01), Corrigan et al.
patent: 5218691 (1993-06-01), Tuma et al.
patent: 5343426 (1994-08-01), Cassidy et al.

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