Printing – Stenciling – Processes
Reexamination Certificate
2001-03-07
2002-09-03
Yan, Ren (Department: 2854)
Printing
Stenciling
Processes
C101S126000, C228S180220, C427S096400
Reexamination Certificate
active
06443059
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 90,102,584, filed Feb. 7, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a bumping process. More particularly, the invention relates to a soldier screen printing process that is performed during bumping process.
2. Description of the Related Art
As the era of information technology progresses, the transmission or processing of information and documents through electronic products are commonly carried out in business processing. Accompanying the progress of technology, many commercial products with more convenient features are promoted, as mobile phones, computers, audio-video articles, while the emphasis is made to miniaturization.
In that present context, integrated circuit packaging technology, accompanying the integrated circuit manufacturing technology, tends to high density of manufactured products. Consequently, many high pin count packaging structures and high density of chip scale packaging (CSP) structures are developed. Flip chip technology, because its guiding principle is mounting and connecting directly the chip to the carrier through a plurality of bumps, which thus can shorten the conductive path while the area of the package is also reduced, is thus substantially employed in chip scale packaging (CSP). In order to improve the throughput and convenience of packaging processes, wafer level packaging is also a presently trend of development using flip chip technology.
Flip chip technology principally consists of forming conductive bumps on the chip I/O bonding pads, the chip is then flipped to be connected to a carrier through the conductive bumps. Such a type of connection structure should be distinguished from that of wire bonding, an advantage over wire bonding being various arrangements of I/O bonding pads, such as matrix arrangement or interlace arrangement, and providing the shortest distance between the chip and the substrate. Other advantages among which reduced surface area, high count of I/O bonding pads, a short signal transmission path and easy control of noise, are characteristic of flip chip packages.
In flip chip technology, the conductive bumps are conventionally formed above the bonding pads through solder screen printing or plating processes.
Referring now to FIG.
1
and
FIG. 2
, there are shown schematic views illustrating a conventional solder screen printing process in wafer bumping.
FIG. 1
is a schematic top view showing a wafer with a plurality of chips formed thereon, and
FIG. 2
is a schematically cross-sectional view illustrating the wafer of
FIG. 1
at an intermediary starting stage before solder screen printing process. First, a wafer
100
is provided, with a plurality of chips
102
formed thereon. Each of the chips
102
has a plurality of bonding pads
104
formed thereon, while a passivation layer
106
covers the chips
102
except for the bonding pad
104
locations that are exposed by the passivation layer
106
. An under bump metal (UBM) structure
108
is formed respectively on each of the bonding pads
104
. Then, a stencil
110
with a plurality of openings
112
formed therein is arranged on the chips
102
in such a manner that the openings
112
are respectively aligned with the bonding pad
104
locations, thereby exposing the locations where solder bumps are to be subsequently formed. Then, by dint of a scraper
114
, a solder paste
116
is filled in the openings
112
according to a screen printing method.
A drawback of the conventional solder screen printing process as described above is a nonuniform thickness of the solder paste that is formed in the openings
112
. As a result, the solder bumps that are subsequently formed will also have nonuniform height, which would cause a non-reliable connection of the chip through the solder bumps.
A solution is thus needed to improve the conventional solder screen printing process and overcome at least the issues and drawbacks described above.
SUMMARY OF THE INVENTION
One major aspect of the present invention is to provide a solder screen printing process, wherein a pattern layer is formed on the wafer to define bump locations thereon while the wafer is mounted in a mounting support means. The mounting support means is such that, with the wafer mounted therein, the height of the surface of the pattern layer onto which the solder screen printing process is applied is substantially reduced, such that the solder paste is thereby filled with an uniform thickness.
To attain the foregoing and other objects, the present invention provides a solder screen printing process comprising: providing a wafer that has a plurality of chips formed thereon and a passivation layer that covers the chips, wherein each of the chips has a plurality of bonding pads that each has an under bump metal (UBM) structure formed thereon, wherein the under bump metal (UBM) structure is exposed through the passivation layer; forming a pattern layer on the wafer, wherein the pattern layer has a plurality of first through openings formed therein to define a plurality of locations where a plurality of bumps is to be formed; providing a carrier that has a wafer mounting location thereon; providing a mounting support means that is arranged on the carrier, such that a second opening of the mounting support means of the wafer size exposes the wafer mounting location of the carrier; mounting the wafer in the second opening of the mounting support means; and performing a solder screen printing by filling a solder paste in the first openings of the pattern layer.
By achieving the above solder screen printing process, wherein the mounting support means enables the wafer to be maintained while the height of the surface of the pattern layer is reduced, the solder paste can be filled with an uniform thickness through the screen printing process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5493969 (1996-02-01), Takahashi et al.
patent: 5740730 (1998-04-01), Thompson, Sr.
patent: 5836998 (1998-11-01), Mueller et al.
patent: 5996488 (1999-12-01), Yanagisawa et al.
patent: 6247640 (2001-06-01), Kuwazaki et al.
patent: 6258227 (2001-07-01), Flanigan
Apack Technologies Inc.
J.C. Patents
Yan Ren
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