Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2000-12-04
2002-10-29
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S672000
Reexamination Certificate
active
06472731
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices in general and, more particularly, to a lead frame and method for assembly of micro-series semiconductor packages while providing maximum die bonding area.
BACKGROUND OF THE INVENTION
Thin small outline semiconductor packages such as TSOP, MSOP, and the SCxx package (manufactured by ON Semiconductor) are well known in the art of micro-series semiconductor packaging. Typical in the art is the TSOP 5 package, which generally consists of a five, leaded lead frame having a semiconductor die bonded onto a flag. The flag makes up one of the five leads extending externally from the package. Wire bonds connect the remaining leads to the inputs/outputs of the circuit comprising the die. Molded plastic encapsulates the lead frame to finish the package.
Because wire bonding is utilized in the prior art TSOP packaging techniques, the die mounting area (the aforementioned flag) is limited in size. This is due mainly because of the need to wire bond from the remaining conductive leads to the inputs/outputs of the circuitry comprising the semiconductor die. Hence, the size of the die used in such packages is limited.
Additionally, the die size is limitation mentioned above also limits the power specifications for the die. Thus, the smaller flag, as well as, the smaller die size that can be used reduces the heat dissipation capabilities of such packages. Thus, minimal power devices can only be used in such micro-series semiconductor packages.
Accordingly, a need exists for a lead frame structure and method of wireless bonding permitting maximum die bonding in micro-series semiconductor packaging. The lead frame structure and method should be an inexpensive process for the manufacture of TSOP plastic molded semiconductor package and allow for the semiconductor die size to be maximized to the edge of the interior dimensions of the package.
REFERENCES:
patent: 5554886 (1996-09-01), Song
patent: 6118174 (2000-09-01), Kim
patent: 6133624 (2000-10-01), Asada
patent: 6150709 (2000-11-01), Shin et al.
patent: 2001/0050420 (2001-12-01), Yang
Cao Phat X.
Semiconductor Components Industries LLC
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