Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2003-01-24
2004-05-11
Zarneke, David A. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
Reexamination Certificate
active
06734570
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of carrier substrate fabrication. More particularly, the invention provides a solder bumped substrate for a fine pitch flip-chip integrated circuit (IC) package.
BACKGROUND OF THE INVENTION
The demand for increased IC functionality and performance continues to drive an increase in the number of input/output (I/O) pads on a typical flip-chip IC package. At the same time, there is a rising demand for smaller sized ICs that are suitable for use in portable devices and other space-sensitive applications. As a result, the I/O pads on a typical flip-chip IC package have become increasingly smaller and more finely pitched. That is, there is less and less distance between adjacent I/O pads on a typical flip-chip IC package.
Various techniques for bonding a flip-chip IC package to a carrier substrate are known in this art. Many such techniques, however, are not well-suited for fine pitch flip-chip IC packages, and often are plagued by the formation of solder shorts between adjacent I/O pads.
SUMMARY
A solder bumped carrier substrate for a fine pitch flip-chip IC package includes a substrate material, a conductive layer, a solder mask layer and solder bumps. The conductive layer is fabricated on the substrate material and includes a plurality of circuit traces coupled to a plurality of bonding pads. The bonding pads are arranged to correspond to input/output (I/O) pads on the flip-chip IC package. The solder mask layer is fabricated over the conductive layer and defines a plurality of tapered pad openings that expose the bonding pads. The plurality of tapered pad openings each have a tapered end, and an expanded end and are interdigitated such that the tapered end of each tapered pad opening is adjacent to the tapered end of at least one other tapered pad opening. The solder bumps are coupled to the bonding pads through the tapered pad openings.
A method of fabricating a solder bumped substrate for a flip-chip integrated circuit (IC) package includes the following steps. Providing a substrate material. Patterning a conductive layer on the substrate material that includes a plurality of circuit traces coupled to a plurality of bonding pads, wherein the bonding pads are arranged to correspond to input/output (I/O) pads on the flip-chip IC. Fabricating a solder mask layer over the conductive layer, wherein the solder mask layer defines a pad opening corresponding to each of the bonding pads, and wherein the pad openings defined by the solder mask layer are tapered such that each pad opening includes an expanded end and a tapered end. Printing solder paste onto a portion of each bonding pad that is exposed by the expanded end of the corresponding pad opening. Reflowing the printed solder paste to form solder bumps on each bonding pad.
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Gennum Corporation
Jones Day
Zarneke David A.
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