Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2002-07-24
2004-12-28
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S406000, C438S408000
Reexamination Certificate
active
06835633
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to a method of fabricating a silicon-on-insulator (SOI) wafer containing a gate-quality, thin (on the order of about 30 to about 100 Å) buried oxide (BOX) region. Such wafers are needed for the fabrication of double-gated metal oxide semiconductor field effect transistors (MOSFETS).
BACKGROUND OF THE INVENTION
Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of MOSFET devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease of threshold voltage V
t
in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain regions.
To scale down MOSFET channel lengths without excessive short-channel effects, gate oxide thickness has to be reduced while increasing channel-doping concentration. However, Yan, et al. “Scaling the Si MOSFET: From bulk to SOI to bulk”, IEEE Trans. Elect. Dev., Vol. 39, p. 1074, July 1992, have shown that to reduce short-channel effects for sub-0.05 &mgr;m MOSFETs, it is important to have a backside-conducting layer present in the structure that screens the drain field away from the channel. The Yan, et al. results show that the double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.
The structure of prior art double-gated MOSFETs consists of a very thin insulating layer for the channel, with two gates, one on each side of the channel. The two gates are electrically connected so that they serve to modulate the channel. Short-channel effects are greatly suppressed in such a structure because the two gates very effectively terminate the drain field line preventing the drain potential from being felt at the source end of the channel. Consequently, the variation of the threshold voltage with drain voltage and with gate length of a prior art double-gated MOSFET is much smaller than that of a conventional single-gated structure of the same channel length.
In the prior art, SOI wafers can be formed using a so-called ‘SMART’ cut process. Although SMART cutting can be used in forming a thick buried oxide region, problems arise when SMART cutting is employed in forming a thin buried oxide region (30-100 Å). The reason that SMART cut technology cannot be used in fabricating SOI wafers having thin buried oxide regions is that SMART cut technology relies on the implantation of hydrogen ions in a Si wafer to form a uniform cut upon annealing the wafer at elevated temperatures.
To date, there are no adequate means for preparing the substrates required to fabricate double-gated MOSFET structures. The required substrates needed are mainly SOI wafers having a BOX region on the order of from about 30 to about 100 Å. Since the BOX region in these substrates will act as a backgate dielectric in a double-gated MOSFET structure, a gate oxide quality BOX region is required. Hence, there is continued need for developing a method of preparing SOI wafers having a gate-quality, thin BOX region.
SUMMARY OF THE INVENTION
The present invention relates to a method of forming a SOI wafer that contains a gate-quality, thin buried oxide (BOX) region. The term “thin” BOX region is used herein to denote a BOX region having a thickness of from about 30 to about 100 Å, whereas the term “gate-quality” denotes that the BOX region of the present invention is a thermal oxide which has little or no defects associated therewith. Thermal oxides are generally characterized as an oxide layer that has a surface state charge density of about 10
10
cm
−2
or less.
Specifically, the SOI wafers having a gate-quality, thin BOX region are fabricated in the present invention by utilizing a method which includes the steps of:
forming a substantially uniform thermal oxide film on a Si-containing layer of a silicon-on-insulator substrate, said thermal oxide film having a hydrophilic surface and said substrate having a buried oxide region positioned between said Si-containing layer and an underlaying Si-containing substrate;
positioning a carrier wafer having a hydrophilic surface such that the hydrophilic surfaces of the thermal oxide film and the carrier wafer adjoin each other;
bonding said hydrophilic surfaces together at about room temperature to provide a bonded structure;
annealing said bonded structure to form a sacrificial oxide on exposed Si surfaces of said bonded structure;
selectively removing said sacrificial oxide and said Si-containing substrate from said bonded structure to expose said buried oxide region; and
selectively removing said exposed buried oxide region to provide a SOI wafer that comprises said thermal oxide film sandwiched between the Si-containing layer of the SOI substrate and the carrier wafer.
It is emphasized herein that since the buried oxide region of the original silicon-on-insulator (SOI) substrate is removed by the method of the present invention, the quality of the original buried oxide layer is of no importance to the present invention. Therefore, the present invention can advantageously use, as the initial substrate, a SOI substrate which contains a low-quality buried oxide. That is, scrap SOI substrates having a low-quality buried oxide region, i.e., non-thermal oxide, can be used in the present invention.
In some embodiments of the present invention, the exposed Si-containing layer provided above can be thinned to a predetermined and desired thickness value using repeated oxidation and oxide removal processing steps.
REFERENCES:
patent: 6380046 (2002-04-01), Yamazaki
patent: 6455398 (2002-09-01), Fonstad et al.
patent: 2002/0185684 (2002-12-01), Cambell et al.
Boyd Diane C.
Hanafi Hussein I.
Jones Erin C.
Schepis Dominic J.
Shi Leathen
International Business Machines - Corporation
Le Dung A.
Scully Scott Murphy & Presser
Trepp Robert M.
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