SOI wafers and methods for producing SOI wafer

Details SOI wafers and methods for producing SOI wafer SOI wafers and methods for producing SOI wafer

2000-11-28

2002-10-08

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

C438S458000, C438S455000

Reexamination Certificate

active

06461939

ABSTRACT:

TECHNICAL FIELD
The present invention relates to SOI wafers wherein a silicon oxide film insulator layer is formed in a silicon single crystal wafer, and methods for producing an SOI wafer.
BACKGROUND ART
The so-called SOI (Silicon On Insulator) structure, which comprises an active silicon layer on an electrically insulating silicon oxide film, can provide excellent processing velocity of devices, low power consumption, high breakdown voltage, environmental friendliness etc., and therefore attracts much attention in recent years. As typical production methods of SOI wafers having such an SOI structure, there are the SIMOX (Separation by Implanted Oxygen) method, and the bonding method.
The SIMOX method is a technique that comprises implanting oxygen ions (
16
O
+
) of a high concentration from a surface of a silicon wafer to form a high concentration oxygen ion implanted layer at a predetermined depth in the wafer, and annealing the wafer at a high temperature of, for example, 1100-1300° C. for several hours to convert the high concentration ion implanted layer into SiO
2
that serves as a buried oxide layer (it is also referred to as “BOX” hereafter) of an SOI wafer, and it has an advantage that a uniform SOI layer thickness can be obtained. However, it suffers from a problem that crystallinity of the SOI layer is degraded.
Further, the bonding method is a technique that comprises bonding two silicon wafers via a silicon oxide film. In this method, as described in, for example, Japanese Patent Publication (Kokoku) No. 5-46086 , an oxide film is formed on at least one of the two wafers, the wafers are closely contacted with each other so as not to contain any foreign matters between the surfaces to be bonded and then they are subjected to a heat treatment at a temperature of 200-1200° C. to enhance the bonding strength. Because it enables subsequent grinding and polishing processes of the bonded wafers of which bonding strength is enhanced by the heat treatment, the wafer of the device fabrication side can be processed by grinding and polishing to reduce its thickness to a desired thickness, and thereby SOI layer on which devices are fabricated can be formed.
A bonded SOI wafer produced as described above has advantages of excellent crystallinity of the SOI layer and high reliability of the produced buried oxide layer existing immediately below the SOI layer. However, because a thin film should be formed by grinding and polishing, the operation for producing the thin film takes time, and there are generated material loss. In addition, the uniformity of the film thickness obtained by this method is only in a level of the desired film thickness±about 0.3 &mgr;m. As a method for making a thin film that solves such problems of the bonding method as for uniformity of film thickness, there has been developed a method called hydrogen ion delamination method as disclosed in Japanese Patent Laid-open (Kokai) No. 5-211128.
This hydrogen ion delamination method is a technique that comprises forming an oxide film on at least one of two silicon wafers, implanting at least one of hydrogen ions or rare gas ions into one of the silicon wafers from its upper surface to form a fine bubble layer (enclosed layer) inside the silicon wafer, bringing the ion-implanted surface into contact with the other wafer via the oxide film, then subjecting the wafers to a heat treatment (delaminating heat treatment) to delaminate one of the wafer as a thin film at the fine bubble layer as a cleavage plane (delaminating plane), and further subjecting them to a heat treatment (bonding heat treatment) for firmly bonding them to obtain an SOI wafer. The surface (delaminated surface) of the SOI wafer produced as described above becomes a relatively good mirror surface. However, in order to obtain an SOI wafer having a surface roughness comparable to an ordinary mirror-polished wafer, it is necessary to perform polishing with extremely little stock removal for polishing, called touch polish.
By this method, an SOI wafer having extremely high uniformity of the SOI layer is relatively easily obtained, and in addition, it has an advantage that the material can be used effectively, because the delaminated one of the wafers can be recycled.
Further, this method also enables silicon wafers to directly bond together without an intermediate oxide layer, and it can be used not only for bonding silicon wafers together, but also for bonding a silicon wafer to an insulating wafer such as quartz, silicon carbide, alumina or the like having a different coefficient of thermal expansion by implanting ions into the silicon wafer.
By the way, in addition to the problem concerning the crystallinity of the SOI layer, the wafer produced by the aforementioned SIMOX method suffers from a problem that the interface between the SOI layer and BOX (it may be also referred to as “SOI/BOX interface” hereinafter) would have serious unevenness, and hence characteristics of the fabricated devices may be likely to fluctuate. As a method for solving this problem, Japanese Patent Laid-open (Kokai) No. 7-263538 discloses a method that can reduce an RMS value (Root Mean Square Value: square average and square root roughness), which represents roughness of interface, of about 2 nm to a level of about 0.85 nm.
As for an SOI wafer produced by the bonding method, however, the interface roughness of the SOI/BOX interface has not caused a problem. That is, because the bonded SOI wafer is obtained by bonding two of mirror-polished silicon wafers via an oxide film as described above, the interface roughness of the SOI/BOX interface depends on the surface roughness of the silicon wafers used. The level of surface roughness of silicon wafers currently used for the production of bonded SOI wafers is about 0.15 nm in terms of RMS, and thus the SOI/BOX interface produced by using such wafers have an interface roughness at a level comparable to it. This is considerably excellent level compared with that provided by SIMOX, and hence the interface roughness of the SOI/BOX interface of an SOI wafer produced by the bonding method has not caused a problem.
However, the development of the techniques for making a thin film such as the aforementioned hydrogen ion delamination method drastically progressed the method for forming a thin film of an SOI wafer and improved thickness uniformity thereof, and thus it became well possible to obtain an SOI layer having an extremely small thickness, i.e., 100±10 nm. As a result, it was found that, even if the level of the surface roughness of the SOI layer surface or the interface roughness of the SOI/BOX interface is about 0.15 nm, which had not been conventionally considered a problem, the characteristics of MOS devices fabricated by using the SOI wafer, such as oxide dielectric breakdown voltage, threshold voltage and carrier mobility, might be adversely affected, i.e., they might be fluctuated, for example, if the thickness of the SOI layer became 500 nm or less. The major cause of this phenomenon is considered that the influence of the surface roughness of the SOI layer surface and the interface roughness of the SOI/BOX interface became significant for the film thickness, because the thickness of the SOI layer was made extremely small and the layer was used with uniform film thickness distribution.
DISCLOSURE OF THE INVENTION
Therefore, the present invention was accomplished in view of such problems, and its object is to provide an SOI wafer having surface roughness of the SOI layer surface and interface roughness of the SOI/BOX interface that affect extremely little on the fluctuation of device characteristics of MOS devices fabricated by using the SOI wafer, such as dielectric breakdown voltage, threshold voltage and carrier mobility, and a method for producing the same.
In order to achieve the aforementioned object, the present invention provides an SOI wafer wherein surface roughness of an SOI layer surface of the SOI wafer is 0.12 nm or less in terms of RMS value.
Since the level of such an excellent surfa

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