SOI substrate and fabrication process therefor

Details SOI substrate and fabrication process therefor SOI substrate and fabrication process therefor

1997-03-28

1999-06-01

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

438404, 438405, 438413, 438977, 148 333, H01L 2176

Patent

active

059096268

ABSTRACT:
After partially burying an insulation layer in a first single-crystalline silicon substrate, and flattening, the first single-crystalline silicon substrate and a second single-crystalline substrate are formed with a low impurity concentration epitaxial layer. By grinding and polishing the first single crystalline silicon substrate, an ultra thin film SOI layer having thickness of about 0.1 .mu.m is formed. On the ultra thin film SOI layer, an insulation layer 8 for isolation is formed. Thus, an SOI substrate for integrating the power element and a control circuit element including the ultra thin film SOI layer in one chip can be provided.

REFERENCES:
patent: 5356827 (1994-10-01), Ohika
patent: 5476809 (1995-12-01), Kobayashi
patent: 5529947 (1996-06-01), Okonogi
patent: 5573972 (1996-11-01), Kobayashi
patent: 5688702 (1997-11-01), Nakagawa et al.
Nakagawa et al., "500VC Three Phase Inverter ICs Based on a New Dielectric Isolation Technique", Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, pp. 328-332.

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