Soi small signal terminated hysteresis receiver

Details Soi small signal terminated hysteresis receiver Soi small signal terminated hysteresis receiver

2000-05-30

2001-07-10

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S021000, C326S086000

Reexamination Certificate

active

06259269

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to terminators which are applicable to metal oxide semiconductor on insulator (MOS-soi) with triple wells integrated circuit technology and which are particularly useful for terminator networks.
U.S. Ser. No. 09/580,290, filed May 30, 2000, entitled: CMOS Small Signal Terminator and Network, naming David T. Hui, inventor; and
U.S. Ser. No. 09/583,187, filed May 30, 2000, entitled: SOI SMALL SIGNAL TERMINATOR AND NETWORK, naming David T. Hui, inventor; and
U.S. Ser. No. 09/583,185, filed May 30, 2000, entitled: Method for use with a Terminator and network, naming David T. Hui, inventor; and
U.S. Ser. No. 09/580,942, filed May 30, 2000, entitled: CMOS Small Signal Switchable Adjustable Terminated Hysteresis Receiver, naming David T. Hui, inventor; and
U.S. Ser. No. 09/580,289, filed May 30, 2000, entitled: CMOS Small Signal Terminated Receiver, naming David T. Hui, inventor; and
U.S. Ser. No. 09/583,055, filed May 30, 2000, entitled: CMOS Small Signal Switchable Terminator Network, naming David T. Hui, inventor, and
U.S. Ser. No. 09/583,186, filed May 30, 2000, entitled: CMOS Small Signal Switchable Adjustable Impedence Terminator Network, naming David T. Hui, inventor; and
U.S. Ser. No. 09/580,789, filed May 30, 2000, entitled: CMOS Small Signal Switchable and Adjustable Terminator Network, naming David T. Hui, inventor; and
U.S. Ser. No. 09/583,188, filed May 30, 2000, entitled: CMOS Small Signal Switchable Impedence and Voltage Adjustable Terminator Network, naming David T. Hui, inventor; and
U.S. Ser. No. 09/580,805, filed May 30, 2000, entitled: CMOS Small Signal Switchable Impedence and Voltage Adjustable Terminator Network and Receiver Integration, naming David T. Hui, inventor; and
U.S. Ser. No. 09/583,680, filed May 30, 2000, entitled: CMOS Small Signal Switchable Impedence and Voltage Adjustable Terminator with Hysteresis Receiver Network, naming David T. Hui, inventor; and
U.S. Ser. No. 09/580,802, filed May 30, 2000, entitled: SOI Small Signal Terminated Receiver, naming David T. Hui, inventor.
This related application(s) and the present application are owned by one and the same assignee, International Business Machines Corporation of Armonk, New York.
The descriptions set forth in these co-pending applications are hereby incorporated into the present application by this reference.
TRADEMARKS
S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, New York, U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
For signal interfaces between devices terminators have been used, as described for instance in U.S. Pat. No. 4748426: entitled “Active termination circuit for computer interface use”, granted May 31, 1988 to Alexander Stewart for Rodime PLC, in an active termination circuit for a computer interface for reducing line reflection of logic signals. Such terminators have used a first and second resistor combination to permanently connect to a signal line that couples a plurality of peripheral devices to one another. The other ends of the first and second resistors are connected through a switching device to a positive voltage supply line and to logic ground, respectively. When termination of multiple devices was required, a plurality of resistor combinations were provided but on/off control of the switch in this example was achieved by one control that is located remote from the termination circuit systems. Integrated circuit interconnection structures have also used precision terminating resistors, as illustrated by U.S. Pat. No. 4,228,369, granted in October, 1980 to Anantha et al. for IBM.
As will be illustrated for chip interconnection, when resistor terminators are used in thin film semiconductor integrated circuits such as those used in metal oxide semiconductors (e.g. CMOS) today, they create hot spots which cannot be adequately cooled, so such resistor terminator circuits which create hot spots cannot be used in metal oxide semiconductor applications to provide terminators for chip to chip connections on chips using IBM's new sub-micron MOS (CMOS) technologies where because of the high currents used in these networks it is difficult or impossible to meet all the cooling and reliability requirements required for commercial performance. It has become necessary to invent a solution to interfacing devices which can be used in such environments on chips, and used for terminators in networks of chips and devices where there is a need to transmit digital data therebetween without overshoot and undershoot in signal transmission between the chips and devices or systems. These connections need to operate at a faster speed, accommodating data rate speeds ranging into hundreds of Mhz and Ghz.
The creation of a terminator which particularly may be fabricated for high speed metal oxide semiconductor on insulator (MOS-soi) applications with triple wells in integrated circuits is needed.
SUMMARY OF THE INVENTION
The preferred embodiment of the invention provides a CMOS small signal integrated terminated hysteresis receiver for a terminator network which allows manufacture with in high speed metal oxide semiconductor on insulator (MOS-soi) with triple wells integrated circuit applications, and provides that upper and lower control devices of a reference circuit are respectively connected to vdd and ground respectively to eliminate the floating body effect and enabling the setting up of a well balanced threshold voltage between the logic levels of a terminator for a network, and to implement hysteresis in the network receiver, so that maximum noise tolerance between logic levels can be achieved for this network and digital system. The hysteresis receiver can receive small signals properly. The receiver has enlarged noise tolerance between upper and lower logic levels.
The terminator network is adapted for MOS that can match the characteristic impedance of the line.
The present invention also provides a terminator network which is fast and suitable for small signal swings and may also in a mixed technologies communication.
The combined terminator and receiver network has low current flow and low power consumption.
Still another feature of the present invention is that a terminator network provides ESD protection at the input of an attached circuit.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.
DESCRIPTION OF THE DRAWINGS
FIG. 1
illustrates the prior art Resistor Terminator Network.
FIG. 2
illustrates the present invention SOI-CMOS SMALL SIGNAL TERMINATED HYSTERESIS RECEIVER NETWORK.
FIG. 3
is a graph having two curves depicting input currents as a function of the input voltages for the CMOS small signal terminator network constructed according to the present invention and a ideal
50
ohm terminator.
FIG. 4
is a graph having curves depicting the input current as a function of the input voltages for the CMOS small signal terminator constructed according to the present invention and curves of the upper and lower power supply currents as a function of the input voltage.
FIG. 5
is a graph having curves depicting the input current as a function of the input voltages for the CMOS small signal terminator constructed according to the present invention and curves of its currents to the upper and lower power supplies as a function of the input voltages. Also having curves of the corresponding input current, and the currents to the upper and lower power supplies for an split resistor terminator as in the prior art.
FIG. 6
is a graph having curves of the power consumption as a function of input voltages for the CMOS small signal terminator constructed according to the present invention and the power consumption of a split resistor as in prior art.
FIG. 7
is a graph with a curves showing the output voltage as a function of input voltages for the CMOS s

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