SOI semiconductor device with reduced topography above a...

Details SOI semiconductor device with reduced topography above a... SOI semiconductor device with reduced topography above a...

2010-10-28

2011-11-01

Brewster, William M. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S691000, C438S756000

Reexamination Certificate

active

08048726

ABSTRACT:
In sophisticated SOI devices, circuit elements, such as substrate diodes, may be formed in the crystalline substrate material on the basis of a substrate window, wherein the pronounced surface topography may be compensated for or at least reduced by performing additional planarization processes, such as the deposition of a planarization material, and a subsequent etch process when forming the contact level of the semiconductor device.

REFERENCES:
patent: 6716679 (2004-04-01), Bae
patent: 2001/0023097 (2001-09-01), Huang
patent: 2008/0268585 (2008-10-01), Gehring et al.
patent: 2009/0194842 (2009-08-01), Ohara
patent: 102006041006 (2008-03-01), None
patent: 102007004859 (2008-08-01), None
patent: 102007057688 (2009-06-01), None
patent: 112007001725 (2009-06-01), None
patent: 102008007002 (2009-08-01), None
Translation of Official Communication from German Patent Office for German Patent Application No. 10 2010 001 400.1-33 dated Oct. 18, 2010.

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