Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – And gettering of substrate
Reexamination Certificate
2003-01-17
2004-12-14
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
And gettering of substrate
C438S407000, C438S473000
Reexamination Certificate
active
06830986
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an SOI semiconductor device employing an SOI substrate and a method for producing the same.
In production of semiconductor devices, high purity semiconductor substrates are used, but heavy metals slightly contained in a semiconductor substrate cause junction leakage in a semiconductor element, or a reduction in the withstand voltage of a gate oxide film. Therefore, the presence of heavy metals is not preferable.
With respect to such heavy metal contamination, in general, an approach called “gettering” is used to capture heavy metals to keep the heavy metals away from a semiconductor device, and thus the heavy metals are prevented from affecting the characteristics of a semiconductor device to be produced. A specific example of this approach is a brush damage method. In this method, a brush damage is caused on the back face of a semiconductor substrate to let this damaged layer capture heavy metals, so that the heavy metals are prevented from affecting the characteristics of a semiconductor element.
However, when producing an SOI semiconductor device employing an SOI substrate, this method cannot be used, because in SOI semiconductor devices, a semiconductor element is formed in an SOI active layer separated from a semiconductor substrate by a buried oxide film. That is to say, some heavy metals cannot pass through the buried oxide film, so that the damaged layer formed on the back face of the semiconductor substrate cannot prevent heavy metal contamination. Therefore, there is a demand for development of a gettering method for heavy metals suitable for SOI semiconductor devices.
A gettering method for an SOI semiconductor device that can solve this problem is disclosed, for example, in Japanese Laid-Open Patent Publication No. 2000-315736. A conventional SOI semiconductor device will be described with reference to FIG.
18
.
FIG. 18A
shows the planar structure of a CMOS transistor of a conventional SOI semiconductor device, and
FIG. 18B
shows the cross-sectional structure taken along line Y-Y′ in FIG.
18
A.
In the structures shown in
FIGS. 18A and 18B
, an n-type semiconductor layer
103
that will serve as an active layer of an SOI substrate is formed on a semiconductor substrate
101
that is a supporting substrate in an SOI substrate via a silicon oxide film
102
that is a first insulating film. The n
−
-type semiconductor layer
103
is isolated in the form of an island by dielectrics, using the silicon oxide films
102
and
105
. More specifically, an isolating groove
104
that reaches up to the buried silicon oxide film
102
is formed by etching, and then the silicon oxide film
105
serving as an insulating film is formed on the side wall portion of the isolating groove
104
. Then, a polysilicon layer
106
is buried and thus the n
−
-type semiconductor layer
103
is isolated in the form of an island by the silicon oxide film
102
and the silicon oxide film
105
.
In the thus formed island-shaped n
−
-type semiconductor layer
103
, an n-type semiconductor layer
122
serving as an N well of a P channel MOS transistor, a p-type semiconductor layer
123
serving as a P well of an N channel MOS transistor, and a highly doped impurity diffusion region (p
+
layer)
110
for the gettering of heavy metals are formed. In other words, the highly doped impurity diffusion region (p+layer)
110
is formed in each of a plurality of n
−
-type semiconductor layers
103
isolated in the form of an island. Furthermore, gate oxide films
125
a
and
125
b
, gate electrodes
124
a
and
124
b
, p
+
-type semiconductor layers
126
a
and
126
b
for forming a drain region and a source region of a P channel MOS transistor, and n
+
-type semiconductor layers
127
a
and
127
b
that will serve as a drain region and a source region of an N channel MOS transistor are formed. Further, wires are formed in this structure and thus a CMOS transistor is produced.
In this CMOS transistor, when the highly doped impurity diffusion region
110
is formed of boron, which is a p type impurity, and the concentration on the surface thereof is 1×10
18
atoms/cm
3
or more and 5×10
20
atoms/cm
3
or less, then the gettering of heavy metals is achieved by the highly doped impurity diffusion region
110
, and thus junction leakage and reduction of the withstand voltage of gate oxide films can be prevented.
However, the inventors of the present invention found the following problem. In the above-described conventional SOI semiconductor device, crystal defects occur in the periphery of the captured heavy metals, so that it is necessary to space the highly doped impurity diffusion region
110
apart from the PN junction by a sufficient distance, which increases the size of a single semiconductor element, and consequently the size of a semiconductor chip is increased. That is to say, in the above-described SOI semiconductor device, the highly doped impurity diffusion region
110
is formed in the same island isolated by insulating films in which a semiconductor element is formed (or the highly doped impurity diffusion region
110
is formed very near an active region). Therefore, the size of the semiconductor element is increased. In the above publication, a method for forming the highly doped impurity diffusion region
110
straddling the isolating groove
104
that forms an isolated region is also proposed. However, in this case, since the highly doped impurity diffusion region
110
is spread in the horizontal direction at the time of diffusion, the gettering layer (the impurity diffusion region
110
) is spread up to the inside of the semiconductor element. Therefore, as a result of ensuring the distance from the impurity diffusion region to the PN junction, a single semiconductor element becomes large, so that the entire semiconductor chip becomes large.
SUMMARY OF THE INVENTION
Therefore, with the foregoing in mind, it is a main object of the present invention to provide a compact SOI semiconductor device and a method for producing the same.
An SOI semiconductor device of the present invention includes at least an SOI substrate including an insulating film and a semiconductor layer formed on the insulating film; and an active semiconductor element formed on the semiconductor layer. The active semiconductor element is formed in an element formation region surrounded by an isolating region for isolating the semiconductor layer in a form of an island. A gettering layer containing a high concentration impurity is formed in a portion of the semiconductor layer excluding the element formation region in which the active semiconductor element is formed, and the gettering layer is not formed in the element formation region in which the active semiconductor element is formed.
It is preferable that the surface concentration of the high concentration impurity in the gettering layer is 1×10
18
atoms/cm
3
or more.
It is preferable that a plurality of active semiconductor elements are formed in the semiconductor layer, and all the active semiconductor elements are positioned within a distance of 1.5 mm from the gettering layer.
In one preferable embodiment, at least one of an N type well and a P type well is formed in the element formation region, and a depth of the gettering layer is substantially the same as or deeper than that of the well.
In one preferable embodiment, a plurality of active semiconductor elements are formed in one of the element formation regions, and the gettering layer is formed outside the isolating region surrounding the element formation region.
In one preferable embodiment, the gettering layer is provided apart from the isolating region.
In one preferable embodiment, the SOI substrate includes a silicon substrate, the insulating film formed on the silicon substrate, and an SOI active layer formed on the insulating film. The semiconductor layer is an SOI active layer made of silicon. The SOI active layer includes at least a transistor as the active semico
Inoue Masaki
Nisimura Hisaji
Satoh Yoshinobu
Yamashita Katsushige
Yamazaki Hiromu
Fourson George
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Toledo Fernando L.
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