Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-03-04
2009-06-09
Warren, Matthew E (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S349000, C257S396000, C257SE27112
Reexamination Certificate
active
07544999
ABSTRACT:
In one illustrative embodiment, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate. In further embodiments, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, performing at least one oxygen implant process after the gate electrode and the protective layer are formed to introduce oxygen atoms into the bulk substrate to thereby form a plurality of oxygen-doped regions in the bulk substrate, and performing at least one anneal process to convert the oxygen-doped regions to dielectric regions comprised of silicon dioxide in the bulk substrate. In one illustrative embodiment, the device comprises a gate electrode formed above an SOI structure comprised of a bulk substrate, a buried insulation layer, and an active layer, and a plurality of dielectric regions comprised of silicon dioxide formed in the bulk substrate, the dielectric regions being self-aligned with respect to the gate electrode.
REFERENCES:
patent: 5510640 (1996-04-01), Shindo
patent: 5608252 (1997-03-01), Nakato
patent: 6103569 (2000-08-01), Teo et al.
patent: 6407428 (2002-06-01), Krishnan et al.
patent: 6441436 (2002-08-01), Wu et al.
patent: 2001/0011756 (2001-08-01), Yu
patent: 2001/0020722 (2001-09-01), Yang
patent: 2002/0063286 (2002-05-01), Wu et al.
Wolf and Tauber, Silicon Processing, vol. 1, Lattice Press, Sunset Beach, CA, pp. 321-322.
Fuselier Mark B.
Wei Andy C.
Wristers Derick J.
Advanced Micro Devices , Inc.
Warren Matthew E
Williams Morgan & Amerson P.C.
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