Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-05-14
2002-10-08
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S351000, C257S352000, C257S353000
Reexamination Certificate
active
06462379
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application is related to Japanese patent application No. HEI 10-141487 filed on May 22, 1998 whose priority is claimed under 35 USC §119, the disclosure of which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a SOI semiconductor device and a method for manufacturing the same, and more particularly to a SOI semiconductor device in which driving capability in an active state is improved and electric current consumption in a standby state is reduced, and a method for manufacturing the same.
2. Description of the Related Art
In recent years, as a substrate to be used for achieving high speed operation and high integration, a so-called SOI substrate, which is a substrate including a very thin semiconductor layer formed on a buried dielectric film, such as a substrate having a single crystal silicon layer, is attracting public attention.
If a complementary MISFET is formed on the SOI substrate, a considerable reduction of any of source-substrate capacitance, drain-substrate capacitance and gate-substrate capacitance is achieved due to the thin single crystal silicon layer, as compared with a conventional MISFET formed on a bulk silicon substrate. Therefore, the high speed operation of an integrated circuit may be achieved. Also, since the buried dielectric film is present, it is possible to form a very narrow device isolation region between two adjacent transistors as compared with the bulk silicon substrate, thereby achieving a further high integration.
On the other hand, the SOI substrate has a drawback that, if the integrated circuit is to be operated with a very low power voltage of 1 V or less, a leak current in the standby state is still large, leading to a large electric current consumption.
In order to solve this problem, Japanese Unexamined Patent Publication Nos, HEI 7(1995)-302908 and HEI 8(1996)-125187 and the like propose a semiconductor integrated circuit including a so-called four-terminal device in which a body contact is formed in each transistor formed on the SOI substrate.
The semiconductor integrated circuit including the four-terminal device is formed on a SOI substrate
40
in which a buried dielectric film
42
and a very thin single-crystal silicon layer
43
are formed on a supporting substrate
41
, as shown in FIG.
12
. On the single-crystal silicon substrate
43
are formed a PMOSFET
47
mainly composed of a gate electrode
46
, a gate dielectric film and source/drain regions
48
, and an NMOSFET
57
mainly composed of a gate electrode
56
, a gate dielectric film and source/drain regions
58
. These FETs are isolated by a device isolation film
44
. Further, body contacts
45
,
55
are formed near the PMOSFET
47
and the NMOSFET
57
.
The four-terminal device in a semiconductor integrated circuit having such a construction has an advantage that an electric potential of a channel portion of each transistor may be controlled by applying a voltage to the body contacts
45
,
55
, whereby a threshold voltage which is one of the factors determining the transistor characteristics, for example, may be dynamically changed.
However, the four-terminal device having the body contacts
45
,
55
has a drawback that the cell area is increased as compared with a conventional MOSFET.
Also, Japanese Unexamined Patent Publication No. HEI 7(1995)-74363 proposes a semiconductor device in which one well contact is formed for a plurality of MOSFETs instead of forming the well contact for each MOSFET, so as to achieve reduction of the cell area.
However, in this semiconductor device, a very thin silicon film having a thickness of 50 to 100 nm is used as the surface semiconductor layer, and moreover, the electric potential of the well is fixed by using the well contact, so that the leak current in the standby state is still large, leading to large electric current consumption.
SUMMARY OF THE INVENTION
The present invention has been made in view of these circumstances and the purpose thereof is to provide a SOI semiconductor device and a method for manufacturing the same in which driving capability in an active state is improved, electric current consumption in a standby state is reduced, and also the cell area of the semiconductor device is kept to a minimum, thereby achieving further scale reduction.
Accordingly, the present invention provides a SOI semiconductor device comprising: a SOI substrate in which a buried dielectric film and a surface semiconductor layer are laminated; at least one well formed in the surface semiconductor layer; and at least one transistor which is formed in the well and has a channel region and source/drain regions in the surface semiconductor layer, wherein the well is completely isolated in the surface semiconductor layer and has a well-contact for applying a bias voltage to the well, the transistor is isolated by a device isolation film formed in a surface of the surface semiconductor layer, the channel region is partially depleted, and the surface semiconductor layer under the source/drain regions is fully depleted.
Also, the present invention provides a method for manufacturing a SOI semiconductor device having the above-mentioned construction, wherein complete isolation of the well is achieved by forming a dielectric film that reaches the buried dielectric film in a predetermined region of the surface semiconductor layer.
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patent: 5440161 (1995-08-01), Iwamatsu et al.
patent: 5463238 (1995-10-01), Takahashi et al.
patent: 5508550 (1996-04-01), Morishita et al.
patent: 5552624 (1996-09-01), Skotnicki et al.
patent: 5652454 (1997-07-01), Iwamatsu et al.
patent: 5770881 (1998-06-01), Pelella
patent: 5801080 (1998-09-01), Inoue et al.
patent: 5959335 (1999-09-01), Bryant et al.
patent: 5963813 (1999-10-01), Manning
patent: 5965917 (1999-10-01), Maszara et al.
patent: 5973363 (1999-10-01), Staab et al.
patent: 5973364 (1999-10-01), Kawanaka
patent: 07074363 (1995-03-01), None
patent: 07302908 (1995-11-01), None
patent: 08125187 (1996-05-01), None
patent: WO 96/28849 (1996-09-01), None
Adan Alberto Oscar
Higashi Kenichi
Chaudhuri Olik
Ha Nathan W.
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