SOI pass-gate disturb solution

Details SOI pass-gate disturb solution SOI pass-gate disturb solution

2000-05-24

2002-12-24

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S155000, C438S157000, C438S156000

Reexamination Certificate

active

06498058

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a Silicon On Insulator (SOI) pass-gate disturb solution, and more particularly pertains to an SOI pass-gate disturb solution for an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) wherein a resistor is connected between the gate and the body if the MOSFET to eliminate the disturb condition.
2. Description of Prior Art
N-type MOSFETs are used as pass-gates in Complementary Metal Oxide Semiconductor (CMOS) circuits for improved density and performance. In the SOI, the body or the substrate of the FET electrically floats. This floating leads to a disturb problem when the source and the drain electrodes are held high for greater than the thermal generation time and the gate is held low, followed by a transition from high to low by the input, which is usually the source. Holes generated in the body prior to the transition are drawn into the source by the low potential during the transition. The bipolar gain, with the source acting as the emitter, the body as the base, and the drain as the collector, results in a current pulse at the output of the pass-gate, which is usually the drain, given by the NPN beta times the body discharge current formula (Cgate×Vdd/Tfall). This current pulse can cause the circuit, which is to be isolated by the pass-gate, to falsely make a transition to the low state.
The current approach to solving this problem is to either increase the noise tolerance of the circuit being isolated by the pass-gate, and/or to add processing steps to reduce the NPN parasitic bipolar gain.
Increasing the immunity of the isolated circuit, called the latch, to this current pulse compromises performance as more current is now required from the pass-gate to complete a desired transition to the low state. Reduction of the NPN gain requires introduction of additional processing steps which involve compromises in leakage and manufacturing heat cycles.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an SOI pass-gate disturb solution.
A further object of the subject invention is the provision of an SOI pass-gate disturb solution for an N-type MOSFET wherein a resistor is connected between the gate and the body of the MOSFET to eliminate the disturb condition.
The present invention eliminates the disturb condition by adding a resistor whose value is approximately 10
10
Ohms−um divided by the width of the pass-gate between the gate and the body of the pass-gate. At this value of resistance, the body will always discharge to the low state before significant thermal charging can occur when the gate is low, and thus prevent accumulation or build up of the body charge when the pass-gate is off. The value of the resistor is high enough such that the current from the gate to the body, when the gate is high and the source and drain are low, is negligible compared to the MOSFET subthreshold current. This circuit also significantly lessens the increase in standby current in SOI MOSFETs since the low gate potential grounds the body and keeps the threshold voltage (Vt) from dropping due to drain avalanche current charging of the body.
In accordance with the teachings herein, the present invention provides a field effect transistor and a method of fabricating in a substrate, and having a source, a drain and a gate, wherein the body of the field effect transistor is electrically floating and the transistor is substantially electrically isolated from the substrate. Pursuant to the present invention a high resistance path is provided coupling the electrically floating body of the field effect transistor to the gate of the field effect transistor. During operation, the high resistance path discharges the body to a low state before significant thermal charging can occur when the gate is low, and thus prevents the accumulation of a charge on the body when the transistor is off.
In greater detail, the resistance of the high resistance path is approximately 10
10
Ohms−um divided by the width of the pass-gate. The high resistance path is sufficiently high such that current from the gate to the body, when the gate is high and the source and drain are low, is negligible compared to the subthreshold current.
The transistor is preferably fabricated in SOI MOSFET, and the circuit significantly lessens an increase in standby current in the SOI MOSFET since the resultant low gate potential grounds the body and prevents the threshold voltage (Vt) from dropping due to drain avalanche multiplication of the current charging the body.


REFERENCES:
patent: 4044373 (1977-08-01), Nomiya et al.
patent: 4586064 (1986-04-01), Esser et al.
patent: 4710791 (1987-12-01), Shirato et al.
patent: 4893158 (1990-01-01), Mihara et al.
patent: 4907053 (1990-03-01), Ohmi
patent: 5160989 (1992-11-01), Houston
patent: 5193058 (1993-03-01), Bassili et al.
patent: 5215931 (1993-06-01), Houston
patent: 5317181 (1994-05-01), Tyson
patent: 5489792 (1996-02-01), Hu et al.
patent: 5498882 (1996-03-01), Houston

Affiliated with

Also associated with

Rating

SOI pass-gate disturb solution does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SOI pass-gate disturb solution, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SOI pass-gate disturb solution will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2984104