SOI MOSFETS exhibiting reduced floating-body effects

Details SOI MOSFETS exhibiting reduced floating-body effects SOI MOSFETS exhibiting reduced floating-body effects

1999-08-18

2004-02-03

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C254S344000, C254S347000, C254S348000, C254S345000, C254S350000, C254S359000

Reexamination Certificate

active

06686629

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a thin film silicon-on-insulator semiconductor device, and more particularly a SOI MOSFET that exhibits reduced floating-body adverse effects. The semiconductor device of the present invention includes a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the device. Furthermore, the present invention relates to a process for fabricating the SOI MOSFET devices of the present invention.
BACKGROUND OF INVENTION
Field effect transistors (FETs) have become the dominant active device for very large scale integration (VLSI) and ultra large scale integration (ULSI) applications in view of the high impedance, high density and low power characteristics of integrated circuit FETs. In fact, much research and development has involved improving the speed and density of FETs and on lowering their power consumption.
The most common configuration of FET devices is the MOSFET which typically comprises source and drain regions in a semiconductor substrate at a first surface thereof, and a gate region therebetween. The gate includes an insulator on the first substrate surface between the source and drain regions, with a gate electrode or contact on the insulator. A channel is present in the semiconductor substrate beneath the gate electrode, and the channel current is controlled by a voltage at the gate electrode.
More recently, in an effort to improve the performance of FET devices such as the threshold voltage and avoiding breakdown of short channel devices, silicon-on-insulator (SOI) technology has become an increasingly important technique. SOI technology deals with the formation of transistors in a relatively thin monocrystalline semiconductor layer which overlies an insulating layer. The insulating layer is typically formed on an underlying substrate which may be silicon. In other words, the active devices are formed in a thin semiconductor on insulator layer rather than in the bulk semiconductor of the device. Currently, silicon is most often used for the monocrystalline semiconductor layer in which devices are formed. However, it will be understood by those skilled in the art that other monocrystalline layers such as germanium or gallium arsenide may be used. Accordingly, any subsequent references to silicon will be understood to include any semiconductor material.
High performance and high density integrated circuits are achievable by using the SOI technology because of the reduction of parasitic elements present in integrated circuits formed in bulk semiconductor. For example, for a MOS transistor formed in bulk, parasitic capacitance is present at the junction between the source/drain regions and the underlying substrate, and the possibility of breakdown of the junction between source/drain regions and the substrate regions also exist. A further example of parasitic elements is present for CMOS technology in bulk, where parasitic bipolar transistors formed by n-channel and p-channel transistors in adjacent wells can give rise to latch-up problems. Since SOI structures significantly alleviate parasitic elements, and increase the junction breakdown tolerance of the structure, the SOI technology is well suited for high performance and high density integrated circuits.
The first application of SOI technology was silicon-on-sapphire. Most recent efforts have been directed toward growing monocrystalline silicon on top of a silicon dioxide layer grown on a silicon wafer. See for example the publications entitled “Ultra-High Speed CMOS Circuits in Thin Simox Films” by Camgar et al, Vol. 89
, IEDM
, pp. 829-832 (1989) and “Fabrication of CMOS on Ultra Thin SOI Obtained by Epitaxial Lateral Overgrowth and Chemical-Mechanical Polishing”, Shahidi et al, Vol. 90
, IEDM
, pp. 587-590 (1990).
Furthermore, SOI technology allows for the mapping of standard advanced technologies into a SOI technology without significant modifications. SOI process techniques include epitaxial lateral overgrowth (ELO), lateral solid-phase epitaxy (LSPE) and full isolation by porous oxidized silicon (FIPOS). SOI networks can be constructed using the semiconductor process of techniques of separation by implanted oxygen (SIMOX) and wafer-bonding and etch-back (SIBOND) because they achieve low defect density, thin film control, good minority carrier lifetimes and good channel mobility characteristics. Structural features are defined by shallow-trench isolation (STI). Shallow-trench isolation eliminates planarity concerns and multidimensional oxidation effects, such as LOCOS bird's beak, thereby allowing technology migration and scaling to sub-0.25 &mgr; technologies.
Although the floating body of a SOI MOSFET provides a number of advantages, including the absence of the reverse-body effect, there are some other problems that such structure poses. Included among the more important problems caused by the device floating body are reduction of the standard saturated threshold voltage, increase of the device OFF current, the pass-transistor leakage current, and large fluctuations in the linear threshold voltage of the device. Accordingly, it would be desirable to reduce the adverse effects of the floating body of SOI devices. The floating-body effects are normally more severe in NMOS devices than in PMOS devices, due to a higher impact ionization rate and normally higher parasitic bipolar gain.
SUMMARY OF INVENTION
The present invention provides for significantly reducing the floating-body problems of SOI devices. In particular, according to the present invention, indium is implanted into the device to provide a pocket halo implant for controlling the short-channel effect and the drain-induced barrier lowering (DIBL). In addition, the indium implant employed according to the present invention degrades the forward characteristics of the body-source diode. In other words, the body-source diode becomes leakier. This higher forward junction leakage in turn reduces the floating-body effects substantially.
More particularly, the present invention is concerned with a thin film silicon-on-insulator semiconductor device which comprises a buried insulation layer located above the layer of the semiconductor material, a semiconductor SOI layer of a first conductivity type located above the buried insulating layer, gate insulating layer located above selected portions of the semiconductor SOI layer, and gate conductor located above the gate insulating layer, source and drain regions of a second conductivity type opposite from the first conductivity type of the semiconductor SOI layer, shallow source and drain extensions of the second conductivity type and pocket halo implant beneath the gate in the channel region of the semiconductor SOI layer, wherein the pocket halo implant is indium implanted at a dosage of about 5E13 to about 1.5E14 and at an energy level of about 60 to about 125 Kev.
Another aspect of the present invention relates to a method for fabricating a thin film silicon-on-insulator semiconductor device. The method comprises providing a structure having a buried insulation layer located above the layer of semiconductor material, semiconductor SOI layer of a first conductivity type located above the buried insulating layer, gate insulating layer located above selected portions of the semiconductor SOI layer, and gate conductor located above the gate insulating layer, shallow source and drain extensions of a second conductivity type opposite from the first conductivity type of the semiconductor SOI layer, and implanting indium ions at a dosage of about 5E13 to about 1.5E14 at an energy level of about 60 to about 125 Kev and at an angle &agr; of about 0° to about 45°, and then annealing the structure at a temperature of about 900° C. to about 1025° C. for about 5 to about 25 seconds to thereby provide a pocket halo implant beneath the gate and in the channel region of the semiconductor SOI layer. The source and drain regions of the second conductivity type are then provided.
Still other objects and advantages of the present

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