Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-04-30
2004-06-22
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S366000
Reexamination Certificate
active
06753579
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having an SOI (Silicon On Insulator) structure, and particularly to control on variations in threshold voltage.
2. Description of the Related Art
A conventional SOI MOSFET device is provided with a silicon layer, a buried oxide film, and a substrate. A first gate electrode, a gate oxide film, a source, and a drain are formed and disposed on the silicon layer.
Such a device structure has been accompanied by a problem that a threshold voltage varies due to variations in the thickness of the silicon layer within a wafer surface. With a view toward correcting the variations, there has been adopted a method of providing a well electrode made conductive to a well (silicon layer) within the well, modifying a bias voltage applied to the well electrode for each device and varying the potential of the silicon layer to thereby set the threshold voltage to a desired value (e.g., see Japanese Patent Application Laid-Open No. Hei 10(1998)-256560).
Since, however, the bias voltage applied to the well electrode is applied between the drain and the substrate in such a device structure, only about 0.6V could be applied under such a condition that no current flowed out in a forward bias state. Thus, a problem was left behind in that the amount of change in threshold voltage was merely obtained only a little.
With a view to greatly securing the amount of the change in threshold voltage, there has been thus disclosed a method wherein a first gate electrode is provided on an upper surface of a silicon layer with a first oxide film interposed therebetween and a second gate electrode is provided on a lower surface thereof with a second oxide film interposed therebetween, respectively, and a voltage for controlling the threshold voltage is applied to the first gate electrode to thereby input a signal to its corresponding second electrode, or a voltage for controlling the threshold voltage is applied to the second gate electrode to thereby input a signal to its corresponding first electrode, whereby the amount of change in threshold voltage is made great (e.g., see Japanese Patent Application Laid-Open No. Hei 10(1998)-256560).
In addition to the above patent documents, there have been disclosed a technology for providing thin-film SOI MOSFETs whose SOIs or gate oxide films are different in thickness, and providing an electrode electrically insulated from a silicon substrate on the silicon substrate of the specific SOI MOSFET thereof (see Japanese Patent Application Laid-Open No. Hei 7(1995)-106579), a technology for forming a thin-film SOI layer on a silicon substrate with a polysilicon film and a silicon oxide film interposed therebetween and configuring a CMOS circuit by use of the thin-film SOI layer (see Japanese Patent Application Laid-Open No. Hei 9(1997)-312401), etc.
A summary of the technology described in the patent document referred to above will be explained using a drawing.
FIG. 6
is a device structure diagram of a conventional SOI MOSFET.
As shown in the drawing, a silicon layer
102
is provided over a substrate
100
with a buried oxide film
101
formed thereon interposed therebetween. A first gate electrode
104
is provided over a surface of the silicon layer
102
, which is located below as viewed in the drawing with a first gate oxide film
103
interposed between the first gate electrode
104
and a channel region in the buried oxide film
101
. Further, a second gate electrode
106
is provided over a surface of the silicon layer
102
, which is located above as viewed in the drawing with a second gate oxide film
105
interposed between the second gate electrode
106
and a channel region in the surface thereof. In such a semiconductor device, the first gate electrode
104
is driven as an input signal gate and the second gate electrode
106
is driven as for threshold voltage control. Alternatively, the second gate electrode
106
is driven as the input signal gate and the first gate electrode
104
is driven as for the threshold voltage control. Driving them in this way allows an increase in the amount of change in threshold voltage.
Owing to the technology of Japanese Patent Application Laid-Open No. Hei 10(1998)-256560, the problem that the threshold voltage varies due to the variations in the thickness of the silicon layer
102
, could be solved by providing the first gate electrode and the second gate electrode in the state of the silicon layer being therebetween as described above, inputting the signal to either one of the gate electrodes and applying the voltage for controlling the threshold voltage to the other gate electrode. Further, the amount of change in threshold voltage could also be greatly ensured.
However, there has been left a problem to be solved that a manufacturing process becomes complex to provide the first gate electrode and the second gate electrode on both sides thereof interposing the silicon layer therebetween, and high-precision processing (polishing or the like) is required.
An object of the present invention is to obtain a device structure capable of avoiding a manufacturing process from becoming complex, and increasing the amount of change in threshold voltage.
SUMMARY OF THE INVENTION
The present invention adopts the following configurations to solve the foregoing.
A first invention provides an SOI MOSFET device characterized in that a second gate electrode is provided on the surface of a silicon layer with an insulating layer interposed between a first gate electrode for a signal input and the silicon layer to apply a predetermined voltage to the silicon layer to thereby control a threshold voltage, in such a manner as to be placed on the same surface of the silicon layer as a surface on which the first gate electrode is disposed.
A second invention provides an SOI MOSFET device characterized in that in the SOI MOSFET device of the first invention, the second gate electrode is provided in plural form.
A third invention provides an SOI MOSFET device characterized in that in the SOI MOSFET device of the second invention, the second gate electrodes are respectively provided at positions to intersect the first gate electrode at both ends of the first gate electrode.
A fourth invention provides an SOI MOSFET device characterized in that in the SOI MOSFET device of the second or third invention, voltages having different values are respectively applied to the respective second gate electrodes.
REFERENCES:
patent: 4849366 (1989-07-01), Hsu et al.
patent: 5619054 (1997-04-01), Hashimoto
patent: 5985733 (1999-11-01), Koh et al.
patent: 6100567 (2000-08-01), Burr
patent: 6383904 (2002-05-01), Yu
patent: 07-106579 (1995-04-01), None
patent: 09-312401 (1997-12-01), None
patent: 10-256560 (1998-09-01), None
L. Manchanda et al. A High-Performance Directly Insertable Self-Aligned Ultra-Rad-Hard and Enhanced Isolation Field-Oxide Technology for Gigahertz Silicon NMOS/CMOS VLSI. IEEE 1989, pp. 651-658.
Duy Mai Anh
Fahmy Wael
Oki Electric Industry CO Ltd.
Rabin & Berdo P.C.
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