SOI MOS field effect transistor and manufacturing method...

Details SOI MOS field effect transistor and manufacturing method... SOI MOS field effect transistor and manufacturing method...

2002-01-14

2003-03-11

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S384000, C257S476000, C257S483000

Reexamination Certificate

active

06531743

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a MOS (Metal Oxide Semiconductor) field effect transistor formed on an insulating substrate or an SOI (Silicon On Insulator) substrate, and a method of manufacturing the same. The present invention relates particularly to a substrate floating effect of an SOI MOS field effect transistor.
2. Description of the Related Art
The formation of a MOS field effect transistor (MOSFET) on an SOI substrate in place of a conventional bulk semiconductor substrate has been carried out in recent years. Forming a MOSFET on a silicon thin film placed on an insulating substrate allows a reduction in parasitic capacity such as junction capacitance, wiring capacitance or the like, the suppression of substrate bias effects, improvements in the establishment of soft errors and latch-up, and the achievement of steep subthreshold characteristics. These exert large effects on improvements in performance, such as a reduction in power consumption of an integrated circuit element, an increase in its operating speed, etc.
FIG. 1
is a cross-sectional view of an SOI MOSFET according to a prior art. In
FIG. 1
, a buried oxide film
2
and an SOI silicon layer are formed over an SOI substrate
1
, and the MOSFET is formed in the SOI silicon layer. The MOSFET comprises a gate insulator
3
, a gate electrode
4
and a source/drain layer
5
. When the source/drain layer
5
has reached the buried oxide film
2
, a body region
7
of the SOI MOSFET is perfectly separated from an external potential and a body potential applied to the MOSFET is held in a non-fixed floating state in particular.
The body potential held in the floating state varies depending on the injection of carriers, the generation and recombination thereof in a depletion layer, capacitive coupling to voltages applied to a gate and a drain which surround the body region, etc., and comes under the influence of a substrate floating effect. Therefore, this will induce the degradation of a source/drain withstand voltage, the occurrence of kinks in current/voltage characteristics of a transistor, a steep gradient characteristic (called self latch or single latch) with an increase in drain voltage upon the dependence of a drain current on a gate voltage, etc. It has been known that problems such as the dependence of a delay time on an input frequency, malfunctioning of a dynamic circuit and a pass gate circuit, etc. arise even upon a circuit operation.
Methods for avoiding the above problems and controlling a body potential have been proposed in large numbers. For instance, a reference NO.1 (IEEE, International Electron Device Meeting 1994, pp.429-432) has described the effectivity and problems of various solutions. A method of providing a contact in a body region to fix a potential, and short-circuiting the body region to a source terminal to thereby solve a substrate floating effect, and a method of forming a recombination center serving as a carrier killer at a source/drain junction end, and extinguishing positive holes stored in the body region through a source, etc. have been discussed. Any of these methods presents a problem of some kind while it provides the effect of reducing the substrate floating effect.
There has also been proposed a method of ion-implanting germanium (Ge) into a sour/drain junction region to thereby control an energy band in a valence band. Forming a mixed crystal of silicon-germanium (SiGe) makes it possible to reduce a source-to-body diffused potential difference (potential barrier) and efficiently pull out or extract positive holes stored in an NMOS body region to the source side. However, a problem remains in that the introduction of Ge of 10% or more becomes difficult due to the occurrence of a crystal defect and the resolvable diffused potential difference is about 0.1V, so that the efficiency is not so good.
Further, a reference NO.2 (Japan Journal of Applied Physics Vol.37(1988), pp.1295-1299) or a reference NO.3 (Technical Report of IEICE, SDM2000-248, pp.55-60(2001)) has proposed a MOSFET having a Schottky barrier junction type source structure, and a MOSFET having a Schottky barrier junction type source/drain structure in place of the conventional MOSFET wherein the source/drain and the body region are separated by the PN junction. It has been shown that the MOSFETs are effective for avoidance of the substrate floating effect.
According to such a method, a Schottky junction made up of high melting-point metal silicide is used, and the height of a Schottky barrier is set lower than a barrier (diffused potential difference) of a PN junction by 0.1V or more. Further, majority carriers (positive holes in the case of NMOS) stored in the body region are efficiently drawn into the source, whereby the substrate floating effect can be resolved. However, this type of structure is accompanied by the problem that since the silicidation of a high melting-point metal is carried out after the formation of gate sidewalls, a region high in resistance is formed between the source and a channel, so that power for driving each MOSFET is reduced.
SUMMARY OF THE INVENTION
The present invention provides an SOI MOS field effect transistor wherein a device isolation region made up of a silicon oxide film, which is perfectly isolated up to the direction of the thickness of an SOI silicon layer is formed, an activation region of the SOI silicon layer, whose only ends are locally thinned, is formed, and a source diffusion layer and a drain diffusion layer of the MOS field effect transistor in the activation region are provided so that according to the silicidation of the SOI silicon layer subsequent to the formation of a high melting-point metal, a Schottky junction is formed only at each end of the activation region and a PN junction is formed at a portion other than each end thereof.


REFERENCES:
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patent: 5877046 (1999-03-01), Yu et al.
patent: 6044011 (2000-03-01), Marr et al.
patent: 6100554 (2000-08-01), Ishikawa et al.
patent: 6225667 (2001-05-01), Buynoski et al.
Technical Report of IEICE, Characteristic of SOI-MOSFET with Ni-Silicide Schottky-Barrier Source/Drain, SDN2000-248(Mar. 2001), pp. 55-60.
Jpn. J. Appl. Phys., vol. 37 (1998), Reduction of the Floating Body Effect in SOI MOSFETs by Using Schottky Source/Drain Contacts, Part 1, No. 3B, Mar. 1998, pp. 1295-1299.
IEDM 94-429, Technology Trends of Silicon-on-Insulator—its Advantages and Probems to be Solved, IEEE, pp. 17.1.1-17.1.4.

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